Vhdl Program

Discussion in 'VHDL' started by sudeep, Feb 6, 2008.

  1. sudeep

    sudeep

    Joined:
    Feb 6, 2008
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    5
    Hi i am BTech final year student doing a project which includes VHDL.I started learning using VHDL primer by bhasker.
    I need a synchronizable program to delay a 40 mhz clock pulse by 7000ns.
    Please do help because i wrote a program with my knowledge but my guide says
    it is not synchronizable it is testbench program.
    So please provide me with a synchronizable VHDL program for that.
    sudeep, Feb 6, 2008
    #1
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  2. sudeep

    sudeep

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    Feb 6, 2008
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    Please do reply i am unable to write synthesazable code please provide with an example i need to proceed with my project or atleast give any wite address to get solutions at.!!
    sudeep, Feb 6, 2008
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  3. sudeep

    scottcarl

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    Sudeep,

    How desperate do you sound!!! You'll get some help if you post your current code, otherwise not many people are simply going to give you the answer. Let's see 1/40Mhz = 20ns. 7000/20 = 350. How about a counter that goes up to 350!!

    Scott
    scottcarl, Feb 6, 2008
    #3
  4. sudeep

    sudeep

    Joined:
    Feb 6, 2008
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    Sorry but im completely new to VHDL and managed to write a testbench program using wait for or 'after'.But im not having any idea how to write statements for synthesizable code.
    sudeep, Feb 7, 2008
    #4
  5. sudeep

    sudeep

    Joined:
    Feb 6, 2008
    Messages:
    5
    advice

    well at last i have written the program and executed well
    again one problem

    i used counters for the program and got it but is there any other method for that if yes please let me know it
    sudeep, Feb 21, 2008
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