I want to implement a (7,3) parallel counter using VHDL. I thought about using 3 full adders but I got derailed when I saw that the output would give out 3 sums and carry out which would make 4 outputs and I need 3. With only 2 full adders, it would not represent 7 inputs.
How would you go about doing it?
**Without just giving me the implementation code, I want to understanddd
Thanks
How would you go about doing it?
**Without just giving me the implementation code, I want to understanddd
Thanks