VHDL: puzzled beginner

[Mark Andrew]

Hi,

just making my first tottering steps in synthesis and have come across
some (for a software person new to hardware) completely unexplainable
behaviour. I have a Spartan 2 based board with some buttons and lights
and am using the free 6.2 version of the Xilinx toolchain. The entity
listed below does exactly what I want when the code tests pbs(0)
against '0': i.e. it changes
the value of the counter (which goes to 4 seven segment displays)
according to whether I have pushed the button or not, and also
illuminates various leds depending on the value of a couple of
switches. But now for the puzzling part. If I test against '1'
instead, I have two effects. Firstly the display starts as "FFFF" and
does not change when I press the button, and secondly, the other bits
of logic after the if statement, going from the switches to the leds,
do not work either, no led is lit at any time.

What on earth can be going on?

Sorry if this is non-vhdl/too vendor-specific/a FAQ - I have been
looking everywhere and found nothing, but possibly do not know where I
should be looking. Would appreciate any hints you guys can throw my
way.

Thanks in advance

--

Mark

-----------------------------------------------------------------------

entity minialu is
Port ( switches : in std_logic_vector(7 downto 0);
leds : out std_logic_vector(7 downto 0);
clk : in std_logic;
pbs : in std_logic_vector(7 downto 0);
counter : out std_logic_vector(15 downto 0));
end minialu;

architecture Behavioral of minialu is
begin
xxx : process (pbs,switches)
begin
if pbs(0) = '0' then -- test for '0' works /test for '1'
fails
counter <= x"1234";
else
counter <= x"FFFF";
end if;
leds(0) <= pbs(0);
leds(7) <= switches(0) or switches(1);
leds(6) <= switches(0) and switches(1);
end process ;
end Behavioral;

 

[Gary Michels]

(e-mail address removed) (Mark Andrew) writes:

Why don't you use your clock?

 

[ALuPin]

You should consider use a synchronous process so that the outputs
become synchronous. What is the frequency of 'clk' ?

What about the input signals? Where do they come from?
Are they synchronous? To which clock?

 

[Mark Andrew]

Thanks for your reply ALuPin,

OK, there is a clock being used in the code to generate the push
button values, but only so they can be debounced. Because I could
think of nothing else to try, I tried synchronising the whole thing
against that clock by changing the beginning of my process as follows:

xxx : process (pbs,switches,clk)
begin
if rising_edge(clk) then

But behaviour remained exactly as before. Furthermore the trivial
behaviour I am trying to get here is essentially asynchronous. It's
not like I need to wait for the system to "settle down" before I go
round again, especially if the pbs have already been debounced for me
- or is it?

 

[ALuPin]

Hi,

what is represented by 'switches'? Are its bit values static that is
they are not changed?

What do you mean with "generate push button values" ?
Do you use some external button and then you synchronize
it within your CPLD/FPGA with a clock? IS that synchronized signal 'pbs' ?
What is the frequency of that clock?
What is the clock frequency of your xxx-process ?

 

[Mark Andrew]

Thanks for your interest AluPIN. I found the problem, which was that I
was missing one of the constraints for the push button input pins. Now
everything is working fine. I think the timing problems still lie in
the future for me