vhdl querry

Discussion in 'VHDL' started by vinodkaruvat, Feb 1, 2011.

  1. vinodkaruvat

    vinodkaruvat

    Joined:
    Feb 1, 2011
    Messages:
    1
    Hello Friends,

    I am new to VHDL and I have a couple of querries. Kindly help me out if possible -

    1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into hardware (gates/mux..etc) using a synthesizer. How is an if-else loop created in hardware? The -f-else is a sequential statement. Will it run/be executed at the same clock cycle or the next ? For eg - in the code shown

    write_req <= '1';
    write_req:process(phy_clk)
    begin
    if rising_edge(phy_clk) then
    if reset_phy_clk = '1' then
    write_req_1 <= '0';
    write_req_2 <= '0';
    else
    write_req_1 <= write_req;
    write_req_2 <= write_req_1;
    end if;
    end if;
    end process p_data_req;

    After how many cycles is write_req_2 asserted ? Can anyone kindly explain this pls? Also, can if-else statements be used to generate/synthesize combinational circuits or only sequential ? Can anyone point me to a doc which shall explain in details how vhdl code is executed(order of execution/timing) and also how it is mapped into hardware ?

    2) What is a latch ?
    fifo_o_addr_temp <= fifo_o_addr when fifo_o_addr_temp /= fifo_o_addr else fifo_o_addr_temp;

    Will doing the above action create a latch ? How so? Is creating a latch in code a good practise or bad?

    Regards,
    Vinod Karuvat.
     
    vinodkaruvat, Feb 1, 2011
    #1
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  2. vinodkaruvat

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    I think in general an if-else block is translated into a multiplexer/set of multiplexers

    In your example, the inner if would be translated into something like:
    (pseudo code)
    Code:
    write_req_1 := mux(sel => reset_phy_clk, 1 => '0', 0 => write_req);
    write_req_2 := mux(sel => reset_phy_clk, 1 => '0', 0 => write_req_1);
    This is an example of a latch:
    Code:
    process(clk)
    begin
    if (clk = '1') then
    if reset_phy_clk = '1' then
    write_req_1 <= '0';
    write_req_2 <= '0';
    else
    write_req_1 <= write_req;
    write_req_2 <= write_req_1;
    end if;
    end if;
    end;
    The point is that, while 'clk' is '1', the values can keep changing; if at some point reset_phy_clk changes while 'clk' is 1, the signal will get the new value.

    In general you want to avoid this; In a sequential design, just use rising_edge(clk) instead.

    Latches often are results of coding mistakes in combinatorial processes:
    Code:
    process(clear)
    begin
    if clear = '1' then
    A <= '0';
    else
    A <= A0;
    B <= B0;
    end if;
    end if;
    end;
    Because B was not updated in one of the paths, the value remains unchanged -- to match this behavior a latch is generated
     
    joris, Feb 1, 2011
    #2
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