Hey!
I'm writing a VHDL code.
I want to use the value of length in the for loop below. I can't ... it is giving me an error ? Can you please tell me how to fix it ?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BSD_Full_Comp is
Generic (n:integer:=8 );
Port(X, Y : inout std_logic_vector(n-1 downto 0);
FZ : out std_logic_vector(1 downto 0));
end BSD_Full_Comp;
architecture struct of BSD_Full_Comp is
Component BSD_BitComparator
Port ( Ai_1 : inout STD_LOGIC; Ai_0 : inout STD_LOGIC;
Bi_1 : inout STD_LOGIC; Bi_0 : inout STD_LOGIC;
S1 : out STD_LOGIC; S0 : out STD_LOGIC
);
END Component;
Signal X1 : std_logic_vector(2*n downto 0);
Signal Y1 : std_logic_vector(2*n downto 0);
Signal Z : std_logic_vector(10*n downto 0);
shared Variable length : integer := n;
shared Variable pow : integer :=0 ;
shared Variable ZS : integer :=0;;
begin
ass : process
begin
while length /= 0 loop
length := length/2;
pow := pow+1;
end loop;
length:= 2 ** pow;
ZS := length - n;
wait;
end process;
Filling_Zeros : For i in 0 to ZS-1 Generate
X1(i)<= '0';
Y1(i)<='0';
End Generate;
Fiiling_Bits : For i in ZS to length-1 Generate
X1(i)<=X(i-ZS);
Y1(i)<=Y(i-ZS);
End Generate;
Compare1: For i in 0 to length/2-1 Generate
BitCompare1: BSD_BitComparator Port map(X1(2*i),X1(2*i+1),Y1(2*i),Y1(2*i+1),Z(2*i),Z(2*i+1));
End Generate;
Compare2: For i in 0 to length/2-2 Generate
BitCompare2: BSD_BitComparator Port map(Z(2*i),Z(2*i+1),Z(2*i+2),Z(2*i+3),Z(2*i+length),Z(2*i+length+1));
End Generate;
FZ(0)<=Z(length);
FZ(1)<=Z(length-1);
end struct;
The Error :
The actual for parameter s0 must denote a static signal name.
There must be away to use the value of length in the loop. How can I make it static ?
I'm writing a VHDL code.
I want to use the value of length in the for loop below. I can't ... it is giving me an error ? Can you please tell me how to fix it ?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BSD_Full_Comp is
Generic (n:integer:=8 );
Port(X, Y : inout std_logic_vector(n-1 downto 0);
FZ : out std_logic_vector(1 downto 0));
end BSD_Full_Comp;
architecture struct of BSD_Full_Comp is
Component BSD_BitComparator
Port ( Ai_1 : inout STD_LOGIC; Ai_0 : inout STD_LOGIC;
Bi_1 : inout STD_LOGIC; Bi_0 : inout STD_LOGIC;
S1 : out STD_LOGIC; S0 : out STD_LOGIC
);
END Component;
Signal X1 : std_logic_vector(2*n downto 0);
Signal Y1 : std_logic_vector(2*n downto 0);
Signal Z : std_logic_vector(10*n downto 0);
shared Variable length : integer := n;
shared Variable pow : integer :=0 ;
shared Variable ZS : integer :=0;;
begin
ass : process
begin
while length /= 0 loop
length := length/2;
pow := pow+1;
end loop;
length:= 2 ** pow;
ZS := length - n;
wait;
end process;
Filling_Zeros : For i in 0 to ZS-1 Generate
X1(i)<= '0';
Y1(i)<='0';
End Generate;
Fiiling_Bits : For i in ZS to length-1 Generate
X1(i)<=X(i-ZS);
Y1(i)<=Y(i-ZS);
End Generate;
Compare1: For i in 0 to length/2-1 Generate
BitCompare1: BSD_BitComparator Port map(X1(2*i),X1(2*i+1),Y1(2*i),Y1(2*i+1),Z(2*i),Z(2*i+1));
End Generate;
Compare2: For i in 0 to length/2-2 Generate
BitCompare2: BSD_BitComparator Port map(Z(2*i),Z(2*i+1),Z(2*i+2),Z(2*i+3),Z(2*i+length),Z(2*i+length+1));
End Generate;
FZ(0)<=Z(length);
FZ(1)<=Z(length-1);
end struct;
The Error :
The actual for parameter s0 must denote a static signal name.
There must be away to use the value of length in the loop. How can I make it static ?