VHDL question about algorithm implementation

Discussion in 'VHDL' started by flatiron@libero.it, Jul 8, 2008.

  1. Guest

    Dear All,
    I'm learning VHDL then may be my question should be easy for you but I
    need some hint to

    go on the subject. At now I've to code a VHDL circut able to drive a
    74HC595 serial-in parallel-out register trough a four lines interface:

    1. SSCLR
    2. SSDAT
    3. SSCLK
    4. SSSTR

    SSCLR will be used to clear the internal 74HC595 register
    SSDAT used as data line, I've to put one bit each clock toggle
    SSCLK clock for the internal 74HC595 shift registers
    SSSTR strobe, used to load the data from the internal registers on the
    output

    At now I'm doing all the task with a microcontroller and a simple C
    code, now I like as exercise to do the same things by using a
    dedicated logic circuit.
    From a logic flow point of view I've to implement this steps:

    dataword = 1;
    For (i=0; i<=15; i++)
    {

    SSCLR <= 0;
    wait;
    SSCLR <= 1;
    For (j=0; j<15;j++)
    {
    SSDAT <= dataword[j];
    wait;
    SSCLK <= 1;
    wait;
    SSCLK <= 0;
    wait;
    }
    SSSTR <= 1;
    SSSTR <= 0;
    dataword << 1;
    }

    By using this code I can load the parallel output of the 74HC595 with
    a word builded with just only one bit set to 1 (I'm using this to test
    all the 74HC595 output one by one).
    My question now is about what architecture is the best to use, a
    PROCESS architecure might be useful in this way? As I've read a
    PROCESS is a collection of statements that are processed in sequential
    way, but also I've see that signals are updated on the process exit
    but into this situation I've to update signal in real time to achieve
    the right behaviour. I'm are right or not about this point?

    Thanks to all
    Powermos
    , Jul 8, 2008
    #1
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