VHDL question - how can I know a clock cycle is over?

[Amit]

Hello group,

I'm working on a VHDL code that gets an input as voltage (a number)
and there are several conditions that I have to consider here.

For example: if voltage is equal or less than 4v the output will have
25 Hz sampling rate and if is more than 6v then sampling rate will be
50 Hz and some other conditions.

Now, what I'm trying to understand is about a specific condition. In
general, there is an input as STATUS (beside the input voltage) which
if it is high then the output will be generated and if not then no
output. However, there is an exception which in there:

If STATUS is on falling edge then the output signal must wait till end
of its clock cycle then it becomes zero. Please correct me if I'm
wrong since I'm new to this:


if clock'event = '0' AND clock = '0' --meaning if clock is on its
falling edge
wait till current clock cycle ends <<<<<<< (LINE A)
stop it

Question: how should I know the clock pulse is over? to set the output
to zero? (in line A)




Your help will be appreciated greatly,

Regards,
amit

 

[KJ]

If STATUS is on falling edge then the output signal must wait till end
of its clock cycle then it becomes zero. Please correct me if I'm
wrong since I'm new to this:


if clock'event = '0' AND clock = '0' --meaning if clock is on its
falling edge
wait till current clock cycle ends <<<<<<< (LINE A)
stop it

Assuming the clock is free running, then the 'end' of every clock cycle is
the same as the 'begining' of the next.

if rising_edge(clock) then
-- Do your 'stop it' stuff here
end if;

KJ

 

[Ahmed Samieh]

if clock'event = '0' AND clock = '0' --meaning if clock is on its

falling edge
wait till current clock cycle ends <<<<<<< (LINE A)
stop it

if (clock'event and clock = '0') then -- = if falling_edge(clock)
then
-- do anything

Question: how should I know the clock pulse is over? to set the output
to zero? (in line A)

replace falling_edge with rising_edge
if (clock'event and clock = '0') then -- if rising_edge(clock) then
-- set output to zero

i suggest this way

fall_process : process(clock, ....)
begin
if falling_edge(clock) then
-- test the inputs
end if;
end process fall_process;
rise_process : process(clock, ....)
begin
if rising_edge(clock) then
-- set output to zero with your conditions
end if;
end process fall_process;

Ahmed Samieh

 

[Ahmed Samieh]

rise_process : process(clock, ....)
begin
if rising_edge(clock) then
-- set output to zero with your conditions
end if;
end process fall_process;

Ahmed Samieh

rise_process : process(clock, ....)
begin
if rising_edge(clock) then
-- set output to zero with your conditions
end if;
end process rise_process;

rise_process insted of fall_process in end process statment.

Ahmed Samieh

 

[Amit]

rise_process : process(clock, ....)
begin
if rising_edge(clock) then
-- set output to zero with your conditions
end if;
end process rise_process;

rise_process insted of fall_process in end process statment.

Ahmed Samieh

Thanks all,

However, it doesn't accomplish what was expecting. Would you please
answer this:

I'm trying to use "WAIT FOR x ns" in a process but the compiler
doesn't accept it in a process block. Any suggestions?

Regards,
amit

 

[Nicolas Matringe]

Amit a écrit :

However, it doesn't accomplish what was expecting. Would you please
answer this:

I'm trying to use "WAIT FOR x ns" in a process but the compiler
doesn't accept it in a process block. Any suggestions?

Hello
You can not use this statement in code intended for synthesis.
You can not use wait statements inside of a process that has a
sensitivity list. A quick workaround is to replace the sensitivity list
with a "wait on ..." statement :

process (<list of signals>) is
begin
...
end process;

becomes

process is
begin
wait on <list of signals>;
...
end process;

Nicolas

 

[Amit]

Amit a écrit :



Hello
You can not use this statement in code intended for synthesis.
You can not use wait statements inside of a process that has a
sensitivity list. A quick workaround is to replace the sensitivity list
with a "wait on ..." statement :

process (<list of signals>) is
begin
...
end process;

becomes

process is
begin
wait on <list of signals>;
...
end process;

Nicolas

Thanks Nicolas,

I tried it but got error on it:

# ** Error: test1.vhd(46): near "<": expecting: STRING IDENTIFIER
# ** Error: test1.vhd(46): near ">": expecting: ';'
# ** Error: vcom failed.

regards,
amit

 

[Jim Lewis]

Amit,
Is this testbench or for synthesis?

For testbench:

process
begin
wait until rising_edge(clk) ; -- stop until a rising edge of clock
... -- do something
wait until rising_edge(clk) ; -- stop until next rising edge of clock
. . . -- do something else 1 clock later

end process ;

For synthesis you need to think more about the waveform you
are trying to create, then if complex, write a statemachine;
if simple, write the register sequence to generate what you
want. Understand that each signal assignment will create a
register and will in effect create a clock cycle delay.


Post more of a specification and we can help more.

Regards,
Jim

 

[JK]

If STATUS is on falling edge then the output signal must wait till end
of its clock cycle then it becomes zero. Please correct me if I'm
wrong since I'm new to this:

if clock'event = '0' AND clock = '0' --meaning if clock is on its
falling edge
wait till current clock cycle ends <<<<<<< (LINE A)
stop it

Question: how should I know the clock pulse is over? to set the output
to zero? (in line A)

Amit,

What do you understand by a process statement?
This may be a basic question but it is needed to start coding in VHDL.
So please answer this question so that we can help you.
How a process statement in VHDL works?

Regards,
JK

 

[Nicolas Matringe]

Amit a écrit :

I tried it but got error on it:

# ** Error: test1.vhd(46): near "<": expecting: STRING IDENTIFIER
# ** Error: test1.vhd(46): near ">": expecting: ';'
# ** Error: vcom failed.

Looks like you need to read more about VHDL before starting writing code.
What if I had written "<insert your own comma-separated list of signals
here>" instead ?

Nicolas