VHDL question - strings in generics...

Discussion in 'VHDL' started by Russell, Aug 19, 2007.

  1. Russell

    Russell Guest

    I used a string in a generic with the '&' operator (as shown in the
    code fragment below), but it does not concatenate (ignores the part
    after the &)

    Do you know if concatenation is not allowed for generics?

    entity mux is

    generic (

    PartNo : string := "12345" & "ABC"

    );

    port (

    TxClk : in std_logic;

    Etc...

    Gives PartNo as "12345"
    Russell, Aug 19, 2007
    #1
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  2. Russell wrote:

    > Do you know if concatenation is not allowed for generics?


    Probably depends on your synthesis tool.

    I've used string concatenation in constants with any problems, but never
    generics as far as I can recall...

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
    Mark McDougall, Aug 20, 2007
    #2
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  3. Russell

    Russell

    Joined:
    Aug 17, 2007
    Messages:
    6
    silly me!

    I had defined it (also) in the test bench at the top level of the simulation
    Russell, Aug 20, 2007
    #3
  4. Russell wrote:
    > I used a string in a generic with the '&' operator (as shown in the
    > code fragment below), but it does not concatenate (ignores the part
    > after the &)


    That tool is broken. Report the bug.

    -- Mike Treseler
    Mike Treseler, Aug 20, 2007
    #4
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