VHDL question (what is the better architecture for this design?)

[flatiron]

I'm learning VHDL then may be my question should be easy for you but I
need some hint to
go on the subject. At now I've to code a VHDL circut able to drive a
74HC595 register trough a four lines interface.
Here below the line signal used to drive the 74HC595 ic.

1. SSCLR
2. SSDAT
3. SSCLK
4. SSSTR

SSCLR will be used to clear the internal 74HC595 register
SSDAT used as data line, I've to put one bit each clock toggle
SSCLK clock for the internal 74HC595 shift registers
SSSTR strobe, used to load the data from the internal registers on the
output

At now I'm doing all the task with a microcontroller and I like to do
the same trough a dedicated logic circuit, from a logic flux point of
view I've to implement these steps:

dataword = 1;
For (i=0; i<=15; i++)
{

SSCLR <= 0;
wait;
SSCLR <= 1;
For (j=0; j<15;j++)
{
SSDAT <= dataword[j];
wait;
SSCLK <= 1;
wait;
SSCLK <= 0;
wait;
}
SSSTR <= 1;
SSSTR <= 0;
dataword << 1;
}

With this circuit I can load the parallel output of the 74HC595 with a
word builded with just only one bit to 1 in order to test all the
output.
My question is about what architecture is the best to use, a PROCESS
architecure might be useful in this way? As I've read a PROCESS is a
collection of statements that are processed in sequential way, but
also I've see that signals are updated on the process exit but into
this situation I've to update signal in real time to achieve the
right
behaviour. I'm are right or not about this point?

Thanks to all
Powermos

 

[Mike Treseler]

My question is about what architecture is the best to use, a PROCESS
architecture might be useful in this way?

There is no other way.

An architecture without a process does nothing.
For synthesis I use a clocked process like this:
--------------------------------------------------------------
architecture synth of my_entity is
begin
main : process(reset, clock) is
-- declarations here
begin -- process template
if reset = '1' then
init_regs; -- procedure call
elsif rising_edge(clock) then
update_regs; -- procedure call
end if;
update_ports; -- procedure call
end process main;
end architecture synth;
--------------------------------------------------------------
For simulation I use an unclocked process like this example ...

main : process is
-- procedure declarations here
constant reps : natural := 8;
begin -- process main: Top level loop invokes top procedures.
init;
for i in 1 to reps loop
timed_cycle; -- procedure call
end loop;
for i in 1 to reps loop
handshake_cycle; -- procedure call
end loop;
coda;
end process main;

.... based on procedures like this
--------------------------------------------------------------
procedure tic is
begin
wait until rising_edge(clk_s);
end procedure tic;
--------------------------------------------------------------
procedure set_bit (signal arg_s : inout std_ulogic) is
begin-- skip tic if already set
if arg_s /= '1' then
arg_s <= '1';
tic;
end if;
end procedure set_bit;

 

[jeppe]

Quess I needed a little "fun" before bedtime.
Im not sure of your description - but I found a datasheet at the net - hope you will find this useful.
More information can be found at my homepage.

-- Engineer:       Jeppe
-- Create Date:    23:08:23 07/08/2008 
-- Module Name:    x74x595 - Behavioral 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- A "true" 595 should have 3-state drivers for Q
entity x74x595 is
    Port ( SSclr : in  STD_LOGIC;
           SSdat : in  STD_LOGIC;
           SSclk : in  STD_LOGIC;
           SSstr : in  STD_LOGIC;
           Q :     out STD_LOGIC_VECTOR (7 downto 0);
           Q7 :    out STD_LOGIC);
end x74x595;

architecture Behavioral of x74x595 is
   Signal Sreg: STD_LOGIC_VECTOR (7 downto 0);
begin
   Q7 <= Sreg(7); -- Always present serial output

   process( SSclk, SSclr)
   begin
        if SSclr='0' then
             Sreg <= (others=>'0'); -- Clear Shiftregister
        elsif Rising_edge( SSclk) then
	 Sreg <= Sreg( 6 downto 0) & SSdat; -- Shift in
        end if;
    end process;
	
    process( SSstr)
    begin
         if rising_edge( SSstr) then
             Q <= Sreg; -- Time to update parallel output
         end if;
    end process;
	
end Behavioral;

PLEASE NOTE - You need two processes in order to implement
two indepent clocksignals.

 

[Jeff Cunningham]

I'm learning VHDL then may be my question should be easy for you but I
need some hint to
go on the subject. At now I've to code a VHDL circut able to drive a
74HC595 register trough a four lines interface.
Here below the line signal used to drive the 74HC595 ic.

1. SSCLR
2. SSDAT
3. SSCLK
4. SSSTR

SSCLR will be used to clear the internal 74HC595 register
SSDAT used as data line, I've to put one bit each clock toggle
SSCLK clock for the internal 74HC595 shift registers
SSSTR strobe, used to load the data from the internal registers on the
output

At now I'm doing all the task with a microcontroller and I like to do
the same trough a dedicated logic circuit, from a logic flux point of
view I've to implement these steps:

dataword = 1;
For (i=0; i<=15; i++)
{

SSCLR <= 0;
wait;
SSCLR <= 1;
For (j=0; j<15;j++)
{
SSDAT <= dataword[j];
wait;
SSCLK <= 1;
wait;
SSCLK <= 0;
wait;
}
SSSTR <= 1;
SSSTR <= 0;
dataword << 1;
}

With this circuit I can load the parallel output of the 74HC595 with a
word builded with just only one bit to 1 in order to test all the
output.
My question is about what architecture is the best to use, a PROCESS
architecure might be useful in this way? As I've read a PROCESS is a
collection of statements that are processed in sequential way, but
also I've see that signals are updated on the process exit but into
this situation I've to update signal in real time to achieve the
right
behaviour. I'm are right or not about this point?

Thanks to all
Powermos

Just transcribing your code of above into a vhdl process will work for
simulation, but will not be synthesizable. AFAIK no synthesizer will
generate hardware from a process with multiple wait statements.
Synthesizable VHDL only contains processes that wait on a clock (for
modeling synchronous logic) or with no wait statements or clock edge
sensing (for combinatorial logic).

To generate synthesizable hardware you should think of the design in
terms of flip flops, combinatorial logic, hardware state machines and so
forth. All synchronous elements run from a common clock. Your task could
be implemented with a simple state machine. See:

http://en.wikipedia.org/wiki/Register_transfer_level
http://en.wikipedia.org/wiki/State_machine

-Jeff

 

[flatiron]

Dear Mike,
thank you for your reply.
Well If I've correctly understand I can use the PROCESS architecture
also to update immediatly the output signals (as into the concurrent
statements), following your example I've to build a first section like
this one:

-----------------------------------
architecture synth of my_entity is
begin
main : process(reset, clock) is
-- declarations here
begin -- process template
if reset = '1' then
init_regs; -- procedure call
elsif rising_edge(clock) then
update_regs; -- procedure call
end if;
update_ports; -- procedure call
end process main;
end architecture synth;
-----------------------------------

in this way when the reset signal is set to 1 at every clock pulse the
update_regs procedure will be called, this procedure should be used to
update the internal registers (FSM) or other stuff then, before the
main process exit, I can update the output signals by using the
update_ports procedure. Of course, if I'm right, the update_regs and
update_ports procedure can be written with concurrent signals
assegnation or should be implemented as PROCESS itself or a mixed of
this type.

I've understanded the point?

Thanks
Powermos

 

[flatiron]

There is no other way.

An architecture without a process does nothing.
For synthesis I use a clocked process like this:

[CUT]

Dear Mike,
thank you for your reply.
Well If I've correctly understand I can use the PROCESS architecture
also to update immediatly the output signals (as into the concurrent
statements), following your example I've to build a first section like
this one:

-----------------------------------
architecture synth of my_entity is
begin
main : process(reset, clock) is
-- declarations here
begin -- process template
if reset = '1' then
init_regs; -- procedure call
elsif rising_edge(clock) then
update_regs; -- procedure call
end if;
update_ports; -- procedure call
end process main;
end architecture synth;
-----------------------------------

in this way when the reset signal is set to 1 at every clock pulse the
update_regs procedure will be called, this procedure should be used to
update the internal registers (FSM) or other stuff then, before the
main process exit, I can update the output signals by using the
update_ports procedure. Of course, if I'm right, the update_regs and
update_ports procedure can be written with concurrent signals
assegnation or should be implemented as PROCESS itself or a mixed of
this type.

I've understanded the point?

Thanks
Powermos

 

[flatiron]

Just transcribing your code of above into a vhdl process will work for
simulation, but will not be synthesizable. AFAIK no synthesizer will
generate hardware from a process with multiple wait statements.
Synthesizable VHDL only contains processes that wait on a clock (for
modeling synchronous logic) or with no wait statements or clock edge
sensing (for combinatorial logic).

To generate synthesizable hardware you should think of the design in
terms of flip flops, combinatorial logic, hardware state machines and so
forth. All synchronous elements run from a common clock. Your task could
be implemented with a simple state machine. See:

http://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/State_machine

-Jeff- Nascondi testo citato

Dear Jeff,
thanks to have point it, my first example is just a flow that I've
from my original code implemented into the microcontroller.

Bye
Powermos

 

[Mike Treseler]

in this way when the reset signal is set to 1 at every clock pulse

Reset is an input that normally happens at power up.

I've understanded the point?

I don't think so. Consider hiring a local tutor.

-- Mike Treseler

 

[Mike Treseler]

Why do you write two versions of the same code? Speed up simulations?

I use the first for synthesis, the second for simulation.

-- Mike Treseler