VHDL question

Discussion in 'VHDL' started by jahaya@gmail.com, Jul 21, 2005.

  1. Guest

    Hello folks,

    I would like to assign a bit in std_logic_vector array to a std_logic
    value, is it permissible? i assume that std_logic_vector IS ARRAY OF
    std_logic type !

    I have mentioned below few piece of my code for illustration:
    (its a part of my testbench)

    I need to sent each bit of the std_logic_vector array at every clock
    cycle.

    --Declarations

    D : std_logic;
    data_in : std_logic_vector(31 downto
    0):="01010000000000000000001100000000"



    Data_inp: process(clk)
    begin
    if (clk'event and clk = '1') then
    for i in 0 to data_in'length loop
    D <= data_in(i);
    end loop;
    end if;
    end process Data_inp;

    ERROR: FATAL ERROR : Index 32 out of range(31 downto 0).
    (I assume it says that we can assign 32 bits to a one bit std_logic)


    Thanks in Advance,
    ALI
     
    , Jul 21, 2005
    #1
    1. Advertising

  2. Guest

    --There was a typo in my previous message

    Hello folks,


    I would like to assign a bit in std_logic_vector array to a std_logic
    value, is it permissible? i assume that std_logic_vector IS ARRAY OF
    std_logic type !


    I have mentioned below few piece of my code for illustration:
    (its a part of my testbench)


    I need to sent each bit of the std_logic_vector array at every clock
    cycle.


    --Declarations


    D : std_logic;
    data_in : std_logic_vector(31 downto
    0):="0101000000000000000000110­0000000"


    Data_inp: process(clk)
    begin
    if (clk'event and clk = '1') then
    for i in 0 to data_in'length loop
    D <= data_in(i);
    end loop;
    end if;
    end process Data_inp;


    ERROR: FATAL ERROR : Index 32 out of range(31 downto 0).
    (I assume it says that we can't assign 32 bits to a one bit std_logic)


    Thanks in Advance,
    ALI
     
    , Jul 21, 2005
    #2
    1. Advertising

  3. john Doef Guest

    a écrit :
    > Hello folks,
    >
    > I would like to assign a bit in std_logic_vector array to a std_logic
    > value, is it permissible? i assume that std_logic_vector IS ARRAY OF
    > std_logic type !

    Sure!

    > I have mentioned below few piece of my code for illustration:
    > (its a part of my testbench)
    >
    > I need to sent each bit of the std_logic_vector array at every clock
    > cycle.
    >
    > --Declarations
    >
    > D : std_logic;
    > data_in : std_logic_vector(31 downto
    > 0):="01010000000000000000001100000000"
    >
    >
    >
    > Data_inp: process(clk)
    > begin
    > if (clk'event and clk = '1') then
    > for i in 0 to data_in'length loop
    > D <= data_in(i);
    > end loop;
    > end if;
    > end process Data_inp;
    >
    > ERROR: FATAL ERROR : Index 32 out of range(31 downto 0).
    > (I assume it says that we can assign 32 bits to a one bit std_logic)

    Just read *your* code: 0 to data_in'length is 0 to 32. And data_in(32)
    is
    not allowed.

    You should write: for i in data_in'range loop

    BTW, the loop is useless and equivalent to:
    D <= data_in (0);

    Just read your code and the error messages.

    JD.
     
    john Doef, Jul 21, 2005
    #3
  4. Guest

    Here you go...
    If you ever synthesize this, you should reset the counter variable
    (index_cnt) before using it, probably by adding a reset input of some
    sort.

    --Declarations
    D : std_logic;
    data_in : std_logic_vector(31 downto
    0):="01010000000000000000001100000000"

    Data_inp: process(clk)
    variable index_cnt : std_logic_vector(4 downto 0) := "00000";
    begin
    if (clk'event and clk = '1') then
    D <= data_in(conv_integer(index_cnt));
    index_cnt := unsigned(index_cnt) + 1;
    end if;
    end process Data_inp;

    The thing you were doing with the loop is pointless as you were
    multiply assigning values to D, in which case only the last assignment
    counts. For loops are different in VHDL than in programming. Also, if u
    use numeric_std as opposed to std_logic_arith you need to replace
    conv_integer with to_integer. Hope this helps
     
    , Jul 21, 2005
    #4
  5. Andy Peters Guest

    wrote:
    > Hello folks,
    >
    > I would like to assign a bit in std_logic_vector array to a std_logic
    > value, is it permissible? i assume that std_logic_vector IS ARRAY OF
    > std_logic type !


    Yes, you can.

    > I have mentioned below few piece of my code for illustration:
    > (its a part of my testbench)
    >
    > I need to sent each bit of the std_logic_vector array at every clock
    > cycle.
    >
    > --Declarations
    >
    > D : std_logic;
    > data_in : std_logic_vector(31 downto
    > 0):="01010000000000000000001100000000"
    >
    > Data_inp: process(clk)
    > begin
    > if (clk'event and clk = '1') then
    > for i in 0 to data_in'length loop
    > D <= data_in(i);
    > end loop;
    > end if;
    > end process Data_inp;
    >
    > ERROR: FATAL ERROR : Index 32 out of range(31 downto 0).
    > (I assume it says that we can assign 32 bits to a one bit std_logic)


    I'm not going to give you the answer straight up. You'll have to work
    out the details for yourself. Given:

    signal data_in : std_logic_vector(31 downto 0);

    What is the value of:

    data_in'length

    ?

    Once you answer that, the cause of the fatal error should be obvious.

    Having said that, your loop still won't do what you want. (Homework:
    Why not?)

    Perhaps a simpler way of doing what you want would be:

    DriveBit : process is
    begin
    for i in data_in'range loop
    D <= data_in(i);
    wait until rising_edge(clk);
    end loop;
    end process DriveBit;

    -a
    --a
     
    Andy Peters, Jul 21, 2005
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    3
    Views:
    4,809
    walala
    Sep 18, 2003
  2. Replies:
    2
    Views:
    8,676
    Jim Lewis
    Mar 21, 2006
  3. dude

    VHDL 2002 vs VHDL 1993

    dude, Mar 23, 2006, in forum: VHDL
    Replies:
    1
    Views:
    1,284
    Nicolas Matringe
    Mar 23, 2006
  4. afd
    Replies:
    1
    Views:
    8,363
    Colin Paul Gloster
    Mar 23, 2007
  5. Kim Enkovaara
    Replies:
    9
    Views:
    1,998
    diogratia
    Oct 16, 2008
Loading...

Share This Page