vhdl range in verilog

Discussion in 'VHDL' started by Ivan, Oct 30, 2009.

  1. Ivan

    Ivan Guest

    Hi,

    how do I use a vhdl range type into a verilog vector?

    eg.
    vhdl:

    type InputRange is
    (
    line01,
    line02,
    line03,
    ....
    );

    and then in verilog I want to use it like this:

    wire [32:0] In_s;
    assign In_s[line03] = other_signal;

    Is it possible?

    thanks
    ivan
    Ivan, Oct 30, 2009
    #1
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  2. Ivan wrote:

    > how do I use a vhdl range type into a verilog vector?
    > eg.
    > vhdl:
    > type InputRange is
    > (
    > line01,
    > line02,
    > line03,
    > ...
    > );



    Last I used verilog,
    enumerations were a do-it-yourself project
    something like:

    parameter line01 = 1,
    line02 = 2,
    line03 = 3;

    Good luck.

    -- Mike Treseler
    Mike Treseler, Oct 30, 2009
    #2
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