VHDL scalar attribute syntax

V

vu_5421

Given :

signal bit_count0 : natural range 0 to CHAN0_BITCNT_MAX - 1;


within a process, is why is the following statement giving me an error
in ModelSim?

if(bit_count0 = bit_count0'high ) then


Of course this compiles no problem :

if(bit_count0 = CHAN0_BITCNT_MAX - 1 ) then


But the first if statement is a little more readable.

Thanks for any help.
 
K

KJ

vu_5421 said:
Given :

signal bit_count0 : natural range 0 to CHAN0_BITCNT_MAX - 1;


within a process, is why is the following statement giving me an error
in ModelSim?

if(bit_count0 = bit_count0'high ) then


Of course this compiles no problem :

if(bit_count0 = CHAN0_BITCNT_MAX - 1 ) then


But the first if statement is a little more readable.

Unfortunately you have to define a new subtype which is a natural in the
range that you want and then use the 'high attribute on the new subtype
instead....I find that kind of annoying too.

KJ
 
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does this help?
vhdlguru.blogspot.com/2010/03/some-tricky-coding-methods-using-vhdl.html
 

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