VHDL Sensitivity (Clock Delay Question)

Discussion in 'VHDL' started by westocl, Mar 7, 2011.

  1. westocl

    westocl

    Joined:
    Mar 7, 2011
    Messages:
    4
    I have a question about whether two processes syncronized by the same clock will alway create a clock delay or can you remove the clock delay by changing the sensitivty list.

    here is an example.

    x1_proc: process(clk)
    begin
    if(clk'event and clk = '1' then
    B <= A;
    end if;
    end x1_proc;

    x2_proc: process(clk)
    begin
    if(clk'event and clk = '1') then
    C <= B;
    end if;
    end proc x2_proc;

    Ok, i can easily see how could take to clock cycles (samples), to traverse A to C, one clock is occured in x1_proc, and one clock occurs in x2_proc;
    now here is the question, say if i said

    x3_proc: process(clk, B)
    begin
    if(clk'event and clk = '1') then
    C <= B;
    end if;
    end x3_proc;

    We have now changed process x3 to be sensitive to the change in B. Does x3, output the value A in just 1 clock and beats x2?? I hear all sorts of things about synthesis tools not caring about sensitivity lists, but in this case i really need to know....

    Please help. Has anyone had any experience with this? I dont have access to tools like 'Chips Scope' to find out enough to be sure., but id like to be SURE. Can somebody try this code in a real and let me/ us all know.

    Thanks
     
    westocl, Mar 7, 2011
    #1
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  2. westocl

    jeppe

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    Mar 10, 2008
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    Location:
    Denmark
    jeppe, Mar 15, 2011
    #2
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  3. westocl

    westocl

    Joined:
    Mar 7, 2011
    Messages:
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    Thanks jeppe for your reply and the link.

    I have one last question having read the link. What about the situation where one assigns a variable to a signal or a signal to a variable??

    Being able to subtly infer a clock delay or not happening has real implications to me. I know i can separate combinational logic and registerd logic, however I am really interested in the particualars of the language.
     
    westocl, Mar 15, 2011
    #3
  4. westocl

    jeppe

    Joined:
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    Location:
    Denmark
    Well - its surely important to understand the difference between Signals and Variables in VHDL.

    I believe the best "book" to learn about this will be: "Evita VHDL" - its an interactive book which you can download for free from the firm.

    In Chapter 6 will you find some great examples.
     
    jeppe, Mar 15, 2011
    #4
  5. westocl

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    A signal gets it's value after 'one delta time' -- in a process that is 'at the end of the execution' of the process code.
    It means that reads of an signal, after assignment to it, get the original value, and following writes effectively discard previous writes.

    The semantics of a variable are different: they immediately get updated to the right-hand value. (taking into account that reads from a signal get the original signal value)


    Just a crazy code (only written for the purpose to have a mix of different assignments)
    Can you figure out the values at the end of the process? Consequently applying these rules should give the right answer
    Code:
    signal s_a, s_b, s_c : std_logic; -- inputs
    signal s_d, s_e, s_f : std_logic;
    
    process(s_a, s_b, s_c) is
      variable v_a, v_b, v_c : std_logic;
      variable v_d, v_e, v_f : std_logic;
    begin
      v_a := s_a;
      v_b := s_b;
    
    
      v_d := s_a xor v_b;
      v_e := s_c and v_d;
      v_f := v_d xor v_e;
    
      s_d <= s_a xor v_b;
      s_e <= s_c and s_d;
      s_f <= s_d xor s_e;
    
    
      v_e := v_f;
      v_d := s_f;
      v_f := s_e;
    
      s_e <= s_f;
      s_d <= s_f;
      s_f <= s_e;
    end process;
    
    In practice I prefer to only read signals into variables as the first statements in a process, and only update signal values at the end of it -- that way it's obvious what is happening.

    I hope that may help!
     
    Last edited: Mar 17, 2011
    joris, Mar 17, 2011
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