vhdl shifting command

Discussion in 'VHDL' started by red, Sep 24, 2008.

  1. red

    red

    Joined:
    Sep 24, 2008
    Messages:
    2
    hi. i am supposed to shift A left by the number of '1's in B. den output it at S.
    i chose to manually shift it. but my codes doesnt seems to work.
    any help?

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;

    entity alu is
    generic (n : natural :=8);

    port( a,b : in std_logic_vector(n-1 downto 0);
    com: in std_logic_vector (3 downto 0);
    cin: in std_logic;
    s: out std_logic_vector(2*n-1 downto 0));
    end entity alu;


    architecture Behavioral of alu is

    begin
    process(com, a, b)

    variable tmpa: std_logic_vector(2*n-1 downto 0);
    variable tmpb: std_logic_vector(2*n-1 downto 0);
    variable tmps: std_logic_vector(2*n-1 downto 0);

    begin

    if(com = "0111") then
    for i in 0 to n-1 loop
    if(b(i) = '1') then
    tmpa := tmpa(2*n -2 downto 0) & cin;
    end if;
    end loop;
    tmps := tmpa;
    end if;

    s <= tmps;
    end process;
    end behavioral;
    red, Sep 24, 2008
    #1
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