VHDL simple process - loop problem

Discussion in 'VHDL' started by pupillo, Aug 25, 2010.

  1. pupillo

    pupillo Guest

    Hi,

    Here below a stupid code to show a problem that I can't understand.
    I have a 8 bit register (myReg) and a clk.
    On each rising edge of clk a process should set myReg(0 to 1) to '0'
    using a for loop and another process (always on each ris. edge) set
    the other bits to '0' as well (remind, it's a STUPID code just for
    understanding).
    When I simulate (tried more simulators) I get zeroes on myReg(0 to 1)
    (ok) but U on the others (2 to 7). WHY?

    If I don't use the for loop (and I simply use assignments) it works.
    If I move the assignments done by the second process, after the end
    loop line of the first process it works.


    Thnaks
    Pupillo



    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;


    entity user_logic is
    end entity user_logic;

    architecture myArch of user_logic is

    signal myReg : std_logic_vector(0 to 7);
    signal myClk :std_logic;

    begin

    REG_0_1_WRITE_PROC : process( myClk ) is
    begin
    if myClk'event and myClk = '1' then
    for index in 0 to 1 loop
    myReg(index)<='0';
    end loop;
    end if;
    end process REG_0_1_WRITE_PROC;


    REG_2_7_WRITE_PROC : process( myClk ) is
    begin

    if myClk'event and myClk = '1' then
    myReg(2 to 7) <= (others => '0');
    end if;
    end process REG_2_7_WRITE_PROC;


    gen_clkrocess begin
    while (true) loop
    myClk<='0';
    wait for 5 ns;
    myClk<='1';
    wait for 5 ns;
    end loop;
    end process;


    end myArch;
     
    pupillo, Aug 25, 2010
    #1
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  2. On Aug 25, 11:24 am, Brian Drummond wrote:

    > alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1;


    Brian, I don't think you can do this. What then happens
    if you attempt to assign to myreg??? Remember that "&"
    is simply a function that returns a result.

    OTOH there may be some way to do it using aggregates.
    Where is Jim Lewis when you need him? :)

    alias myreg : std_logic_vector(7 downto 0) is
    (7 => myreg_2(5)
    ,6 => myreg_2(4)
    , .... ad nauseam ....
    ,2 => myreg_2(0)
    ,1 => myreg_1(1)
    ,0 => myreg_1(0) );

    Even if it works (which I doubt) it's pretty nasty!
    --
    Jonathan Bromley
     
    Jonathan Bromley, Aug 25, 2010
    #2
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  3. pupillo

    pupillo Guest

    On 25 Ago, 13:42, Jonathan Bromley <>
    wrote:
    > On Aug 25, 11:24 am, Brian Drummond wrote:
    >
    > > alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1;

    >
    > Brian, I don't think you can do this.  What then happens
    > if you attempt to assign to myreg???  Remember that "&"
    > is simply a function that returns a result.
    >
    > OTOH there may be some way to do it using aggregates.
    > Where is Jim Lewis when you need him? :)
    >
    >  alias myreg : std_logic_vector(7 downto 0) is
    >    (7 => myreg_2(5)
    >    ,6 => myreg_2(4)
    >    ,  .... ad nauseam ....
    >    ,2 => myreg_2(0)
    >    ,1 => myreg_1(1)
    >    ,0 => myreg_1(0) );
    >
    > Even if it works (which I doubt) it's pretty nasty!
    > --
    > Jonathan Bromley


    I think that the best thing is driving all the bus within the same
    process, however I wonder why a compiler should try to suppose that
    only one process drives all the signals. It looks like going against
    the semantic of vhdl.
     
    pupillo, Aug 25, 2010
    #3
  4. On 8/25/2010 8:52 AM, pupillo wrote:

    > I think that the best thing is driving all the bus within the same
    > process,


    True.

    > however I wonder why a compiler should try to suppose that
    > only one process drives all the signals. It looks like going against
    > the semantic of vhdl.


    But there is only one signal:
    signal myReg : std_logic_vector(0 to 7);

    Use use two vectors or std_ulogic for bits.
    It is easier to combine than slice in vhdl.

    -- Mike Treseler
     
    Mike Treseler, Aug 25, 2010
    #4
  5. pupillo

    pupillo Guest

    I think that you're right.
    For VHDL it'is ONE signal (even though it's a bus), thus driving one
    signal in two process can lead to a undefined behaviour.
    Pupillo


    On 25 Ago, 18:05, Mike Treseler <> wrote:
    > On 8/25/2010 8:52 AM, pupillo wrote:
    >
    > > I think that the best thing is driving all the bus within the same
    > > process,

    >
    > True.
    >
    > > however I wonder why a compiler should try to suppose that
    > > only one process drives all the signals. It looks like going against
    > > the semantic of vhdl.

    >
    > But there is only one signal:
    > signal myReg : std_logic_vector(0 to 7);
    >
    > Use use two vectors or std_ulogic for bits.
    > It is easier to combine than slice in vhdl.
    >
    >      -- Mike Treseler
     
    pupillo, Aug 25, 2010
    #5
  6. On Wed, 25 Aug 2010 08:52:18 -0700 (PDT), pupillo wrote:

    >I think that the best thing is driving all the bus within the same
    >process,


    Yes. Very good for your sanity.

    > however I wonder why a compiler should try to suppose that
    >only one process drives all the signals. It looks like going against
    >the semantic of vhdl.


    Two issues here:
    - all the 'U' values you saw were precisely because you
    had two processes driving the same signa; the problem
    was that one process was unexpectedly driving 'U's,
    because.....
    - a 'for' loop in VHDL is "dynamically elaborated", so the
    for-loop range cannot be used to determine which of a set
    of signals the process drives. Consequently, if you drive
    even one bit of the vector from within that for-loop,
    the whole vector is driven by the process. Search the
    VHDL LRM for the phrase "longest static prefix" to find
    more detail on why this is so.

    The for-loop thing is often quite irritating, especially
    to people who use for-loops for synthesis and expect the
    loop to be statically unrolled. In VHDL that is not what
    happens. For-generate loops, on the other hand, ARE
    statically elaborated and you can use them to drive
    selected bits of a vector while leaving other bits
    undriven - bear in mind that the for-generate is
    actually constructing separate processes for each
    pass of the loop, and each process statically knows
    which part of the vector it's driving. Not so with
    a procedural for-loop; there's just one process, but
    if you use the loop counter as an index into the vector
    then the process doesn't know statically which bits
    it will drive, and must conclude that it's driving
    the whole vector.

    No easy answers, I'm afraid (apart from the sensible
    "just one process" advice). Most people (me included)
    find the LRM description of longest-static-prefix
    quite hard to follow, although it's very precise.
    --
    Jonathan Bromley
     
    Jonathan Bromley, Aug 25, 2010
    #6

  7. >>> alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1;


    > But my posting machine doesn't do VHDL, and my work machine isn't on the
    > internet, so this approach remains untested (here)...


    ModelSim won't compile it, but I haven't had time to
    trawl the LRM to work out exactly what to do instead.
    Given that "A&B" is not a reference-able thing, but rather
    is just the value-result of a function's execution, I
    don't think it will ever be possible to make that happen.

    Aggregates don't seem to work either. Once again, I haven't
    had a chance to work out precisely why, or what you could
    do about it.
    --
    Jonathan Bromley
     
    Jonathan Bromley, Aug 26, 2010
    #7
  8. pupillo

    pupillo Guest

    On 26 Ago, 09:15, Jonathan Bromley <>
    wrote:
    > >>> alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1;

    > > But my posting machine doesn't do VHDL, and my work machine isn't on the
    > > internet, so this approach remains untested (here)...

    >
    > ModelSim won't compile it, but I haven't had time to
    > trawl the LRM to work out exactly what to do instead.
    > Given that "A&B" is not a reference-able thing, but rather
    > is just the value-result of a function's execution, I
    > don't think it will ever be possible to make that happen.
    >
    > Aggregates don't seem to work either.  Once again, I haven't
    > had a chance to work out precisely why, or what you could
    > do about it.
    > --
    > Jonathan Bromley


    OK,
    thanks to all, I will keep in mind your advices
    Pupillo
     
    pupillo, Aug 26, 2010
    #8
  9. pupillo

    Andy Guest

    On Aug 26, 2:15 am, Jonathan Bromley <>
    wrote:
    > >>> alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1;

    > > But my posting machine doesn't do VHDL, and my work machine isn't on the
    > > internet, so this approach remains untested (here)...

    >
    > ModelSim won't compile it, but I haven't had time to
    > trawl the LRM to work out exactly what to do instead.
    > Given that "A&B" is not a reference-able thing, but rather
    > is just the value-result of a function's execution, I
    > don't think it will ever be possible to make that happen.
    >
    > Aggregates don't seem to work either.  Once again, I haven't
    > had a chance to work out precisely why, or what you could
    > do about it.
    > --
    > Jonathan Bromley


    I tend to think of aliases as just a different handle to the same
    object. It does not and cannot rely upon any movement of data. Thus
    you cannot just create an alias that is a vector of disassociated bits
    because those bits are not located together where a vector reference
    will work.

    Andy
     
    Andy, Aug 27, 2010
    #9
  10. On Fri, 27 Aug 2010 08:49:13 -0700 (PDT), Andy wrote:

    >you cannot just create an alias that is a vector of disassociated bits
    >because those bits are not located together where a vector reference
    >will work.


    Agreed, that makes perfect sense, and I've no doubt
    it's what actually happens.

    _A_fortiori_ you can't alias to the value (result)
    of an expression, such as A&B.
    --
    Jonathan Bromley
     
    Jonathan Bromley, Aug 27, 2010
    #10
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