vhdl simulator speed test

Discussion in 'VHDL' started by Account1, Jan 20, 2007.

  1. Account1

    Account1 Guest

    Hi,

    Could you suggest vhdl source files/ or "gate construct" for vhdl simulator
    speed testing? I would like to test only built in function ( like: a<=b and
    c) with standard logic without resoltion function. For example an 1000 bit
    adder or similar, but Im not familiar with it. The best would, when you
    suggest a construct for example adder( N ) with picture or pdf, then I will
    generate an vhdl source file from a C program.

    Thanks
    Attila
    Account1, Jan 20, 2007
    #1
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