VHDL Standards Invitation and Status

[Jim Lewis]

Hi,
The VHDL Standards group is currently working on VHDL 1076-201X.
Currently we are working on developing language change proposals.
Check them out at:
http://www.eda.org/twiki/bin/view.cgi/P1076/CollectedRequirements

Did we miss something? Could the proposals be better?

Join us and help out. We have many tasks that can involve
a wide range of skills. For starters we need users
reviewing proposals and saying, yes if you add that I
will use it. For more experienced VHDL users, we have
proposals that need owners or helpers working on them.
Proposals describe the problem, and identify a solution
to it. After the proposals are done, we need highly
knowledgeable VHDL community members to help convert
the proposals into LRM text. Some may participate in all
tasks, some may only participate in one or two.

Lets face it while standards take time, they take less
time with more participation.

Best Regards,
Jim Lewis
IEEE P1076 VHDL Working Group Chair
VHDL Training Expert, http://www.SynthWorks.com
OSVVM, Chief Architect and Co-founder

 

[GaborSzakacs]

Hi,
The VHDL Standards group is currently working on VHDL 1076-201X.
Currently we are working on developing language change proposals.
Check them out at:
http://www.eda.org/twiki/bin/view.cgi/P1076/CollectedRequirements

Did we miss something? Could the proposals be better?

Join us and help out. We have many tasks that can involve
a wide range of skills. For starters we need users
reviewing proposals and saying, yes if you add that I
will use it. For more experienced VHDL users, we have
proposals that need owners or helpers working on them.
Proposals describe the problem, and identify a solution
to it. After the proposals are done, we need highly
knowledgeable VHDL community members to help convert
the proposals into LRM text. Some may participate in all
tasks, some may only participate in one or two.

Lets face it while standards take time, they take less
time with more participation.

Best Regards,
Jim Lewis
IEEE P1076 VHDL Working Group Chair
VHDL Training Expert, http://www.SynthWorks.com
OSVVM, Chief Architect and Co-founder

I didn't look very deep into the existing requests, but I wonder if
anyone considered bit reversal, for example allowing SLV's defined
as (N downto 0) to be referenced in reverse order (0 to N).

PRO:
Reduces use of loops for intentional bit reversal

CON:
Could happen unintentionally when you thought you had a
signal defined with "downto", when it was actually defined
with "to" causing undesired bit reversal.

 

[Andy]

Rather than allow the reverse range to be used as an index range, I would prefer a standard function(s), such as right_to_left() to return a bit-reversed vector (with reversed range to match.)

Such a fix would have far less impact on tool vendors (and therefore adoption/support) than directly allowing reversed range access of vectors.

I would also prefer such a function NOT be defined for types for which numeric interpretations (arithmetic, conversion between integer/real) are defined in the same standard package. This would allow right_to_left(SLV), even though numeric interpretation of SLV is applied by numeric_std_unsigned.

If a user wants to write their own overloaded function for unsigned, etc. so be it, but it should not be in the numeric_standard package. Especially so for fixed point types, which depend on index values for numeric interpretation.

Andy

 

[Jim Lewis]

Hi Gabor,

I didn't look very deep into the existing requests, but I wonder if

anyone considered bit reversal, for example allowing SLV's defined

as (N downto 0) to be referenced in reverse order (0 to N).



PRO:

Reduces use of loops for intentional bit reversal



CON:

Could happen unintentionally when you thought you had a

signal defined with "downto", when it was actually defined

with "to" causing undesired bit reversal.

We don't have any requests for this. Do you have a specific
use case? This is what is required to initiate a proposal.
Perhaps you want to post this as a separate thread to gauge
the interest level.

I agree with Andy, it would be bad to do this with index ranges,
however, a reverse function would work just as well.
If it were something for broad usage, I would prefer an implicitly
defined function - like "&" which is implicitly defined for all
single dimensional arrays.

Jim