VHDL state machine

Discussion in 'VHDL' started by yannick, Oct 10, 2008.

  1. yannick

    yannick

    Joined:
    Oct 10, 2008
    Messages:
    1
    Hi.

    I had to designed a big (more than 30 states) state machine for my work. I wrote something like :

    if rst = '0' then
    state := init
    out1 <=
    out2 <=
    elsif rising_edge(clk) then
    case state is
    when init =>
    state := ...
    out1 <= ...
    out2 <= ...​
    when ... =>
    state := ...
    out1 <= ...
    out2 <= ...​

    I am not sure about two points :

    1) I wrote it within a single process. It means that state and outputs are changed at the same time. Most of the exemples I saw on the web are using 2, or sometimes 3 process to design a state machine. Is this a problem?

    2) and more important : I declared my state variable as a variable and not as a signal. I looked on the web and cannot find a single exemple where "state" is declare as variable! why am I the only one to do this? is this another problem?

    thank you
     
    yannick, Oct 10, 2008
    #1
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  2. yannick

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi

    vHDL or just HDL = Hardware Description Language means that your try to descripe a functionality, structure, behavioar etc. Its up to the tool to figure out the hardware needed to fit your description.

    1) You should be aware that this description will generate extra F/F for the outputs (please consult the link below) - I would say 2 or 3 processes better but still am I using one ever now and then ;-)

    2) Some people designeres believe that variable lesser worth then signals when it comes to generate F/F's - this not true. The tool will reconize a variable as F/F anyway.

    Your welcome
    Jeppe

    Go to the example below "Serial adder" with 1,2 or 3 processes: http://www.jjmk.dk/MMMI/Exercises/04_Statemachine/No2_Implementation/exer4_2_implemtations.htm
     
    jeppe, Oct 10, 2008
    #2
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