VHDL state machine

Joined
Oct 10, 2008
Messages
1
Reaction score
0
Hi.

I had to designed a big (more than 30 states) state machine for my work. I wrote something like :

if rst = '0' then
state := init
out1 <=
out2 <=
elsif rising_edge(clk) then
case state is
when init =>
state := ...
out1 <= ...
out2 <= ...​
when ... =>
state := ...
out1 <= ...
out2 <= ...​

I am not sure about two points :

1) I wrote it within a single process. It means that state and outputs are changed at the same time. Most of the exemples I saw on the web are using 2, or sometimes 3 process to design a state machine. Is this a problem?

2) and more important : I declared my state variable as a variable and not as a signal. I looked on the web and cannot find a single exemple where "state" is declare as variable! why am I the only one to do this? is this another problem?

thank you
 
Joined
Mar 10, 2008
Messages
348
Reaction score
0
Hi

vHDL or just HDL = Hardware Description Language means that your try to descripe a functionality, structure, behavioar etc. Its up to the tool to figure out the hardware needed to fit your description.

1) You should be aware that this description will generate extra F/F for the outputs (please consult the link below) - I would say 2 or 3 processes better but still am I using one ever now and then ;-)

2) Some people designeres believe that variable lesser worth then signals when it comes to generate F/F's - this not true. The tool will reconize a variable as F/F anyway.

Your welcome
Jeppe

Go to the example below "Serial adder" with 1,2 or 3 processes: http://www.jjmk.dk/MMMI/Exercises/04_Statemachine/No2_Implementation/exer4_2_implemtations.htm
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Similar Threads

MAX6675 VHDL 0
State machine definitions 12
VHDL finite state machine 11
state machine reset 48
Problem With Mealy Sequence Detector 1
pls help me ; vhdl; 0
train ticket machine help needed! 0
2 JK Circuit in VHDL 0

Members online

No members online now.

Forum statistics

Threads
473,744
Messages
2,569,482
Members
44,901
Latest member
Noble71S45

Latest Threads

Top