VHDL Subscripts

[Cameron, Charles B.]

I was surprised to discover that Altera's MaxPlus II interpreted the
signal name z1 as z(1), something I only guessed after extensive head
scratching. I had declared both z and z1 to be of type
standard_logic_vector. Once I renamed the signal z1 as zint, my problem
went away. However, in pursuing the cause of my confusion I have found
no reference that states an equivalence between z1 and z(1). Can
anybody steer me to a reference that addresses this point?

Charles B. Cameron

 

[Nicolas Matringe]

Cameron, Charles B. a écrit:

I was surprised to discover that Altera's MaxPlus II interpreted the
signal name z1 as z(1), something I only guessed after extensive head
scratching. I had declared both z and z1 to be of type
standard_logic_vector. Once I renamed the signal z1 as zint, my problem
went away. However, in pursuing the cause of my confusion I have found
no reference that states an equivalence between z1 and z(1). Can
anybody steer me to a reference that addresses this point?

This is a MaxPlus+II problem, not a VHDL problem (you would probably
encounter it with Verilog too). I suggest to change from MaxPlus+II (now
becoming obsolete) to QuartusII.

 

[Cameron, Charles B.]

Cameron, Charles B. a écrit:



This is a MaxPlus+II problem, not a VHDL problem (you would probably
encounter it with Verilog too). I suggest to change from MaxPlus+II
(now becoming obsolete) to QuartusII.

Many thanks for telling me this. I suspected it, but I couldn't verify
it independently. At my university we use the Altera UP-1 and UP-2
boards with student licenses, which effectively do not expire. I
haven't figured out a way to use Quartus II in the same manner. If
anyone knows how to handle this, too, then we could stop using
MaxPlus+II immediately. I much prefer the Quartus II interface and I've
found that it does a better job at finding fast netlists than MaxPlus+II
does.

Charles B. Cameron