VHDL Synchronizer Function

Discussion in 'VHDL' started by genogiapasetti@gmail.com, Apr 19, 2014.

  1. Guest

    Is there a way to write a VHDL synchronizer function that could be called from a section of sequential code as:

    if sync(clock, a) = '1' then...

    where "a" is a signal from another clock domain and "clock" is the clock in the present domain?

    I've tried

    function sync(clock, in: std_logic) return std_logic is
    variable med, result: std_logic;
    begin
    if clock'event and clock = '1' then
    med := input;
    result := med;
    end if;
    return result;
    end sync;


    The result in the Xilinx simulator is syntactically accepted but is always undefined, no matter how many variations of the above I tried.

    Is there a technique which preserves the convenience of my approach but works?

    Geno
     
    , Apr 19, 2014
    #1
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  2. Dio Gratia Guest

    On Sunday, April 20, 2014 7:19:11 AM UTC+12, wrote:
    > Is there a way to write a VHDL synchronizer function that could be calledfrom a section of sequential code as:
    >
    >
    >
    > if sync(clock, a) = '1' then...
    >
    >
    >
    > where "a" is a signal from another clock domain and "clock" is the clock in the present domain?
    >
    >
    >
    > I've tried
    >
    >
    >
    > function sync(clock, in: std_logic) return std_logic is
    >
    > variable med, result: std_logic;
    >
    > begin
    >
    > if clock'event and clock = '1' then
    >
    > med := input;
    >
    > result := med;
    >
    > end if;
    >
    > return result;
    >
    > end sync;
    >
    >
    >
    >
    >
    > The result in the Xilinx simulator is syntactically accepted but is always undefined, no matter how many variations of the above I tried.
    >
    >
    >
    > Is there a technique which preserves the convenience of my approach but works?
    >
    >
    >
    > Geno


    Local variables in a function are created new each function call. Also note your sequential assignments of med and result don't imply a clock delay between them the value of med is updated immediately. While your simulationmight work it doesn't synchronize.

    You could try a procedure:

    library ieee;
    use ieee.std_logic_1164.all;

    entity foo is
    end entity;

    architecture fum of foo is
    procedure sync (
    signal clk: in std_logic;
    signal a: in std_logic;
    signal med: inout std_logic;
    signal result: inout std_logic
    ) is
    begin
    if clk'event and clk = '1' then
    med <= a;
    result <= med;
    end if;
    end ;

    signal a: std_logic;
    signal clk: std_logic := '0';
    signal med: std_logic;
    signal result: std_logic;
    begin
    SYNCHRO:
    sync (clk,a,med,result);
    EVALUATE:
    process (result)
    begin
    if result = '1' then

    end if;
    end process;

    end architecture;


    Notice this is the equivalent of using a sync component because a proceduredoesn't have a return value, with various restrictions on using signals ina procedure effectively limiting this to one level of hierarchy.

    You might as well create a sync component and use and output signal name that's descriptive (e.g. a_sync).
     
    Dio Gratia, Apr 19, 2014
    #2
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  3. Dio Gratia Guest

    You could note in your function, besides the formal 'in' in 'clock, in:' being illegal (appears to have been intended to be 'clock, input:'), the formal 'clock' hasn't been declared as class signal, meaning as class variable (the default) the expression 'clock'event' is illegal and should result in an error.
     
    Dio Gratia, Apr 20, 2014
    #3
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