VHDL synthesis

Discussion in 'VHDL' started by lightofspace, Oct 21, 2006.

  1. lightofspace

    lightofspace

    Joined:
    Oct 19, 2006
    Messages:
    8
    Hallo,
    I have a problem in understanding the synthsis of VHDL between if and case statement, and when the synthesis use Flip-Flop or latch?
    regards,
    ahmad
     
    lightofspace, Oct 21, 2006
    #1
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