VHDL synthesis

L

lightofspace

Joined
Oct 19, 2006
Messages
8
Reaction score
0
Hallo,
I have a problem in understanding the synthsis of VHDL between if and case statement, and when the synthesis use Flip-Flop or latch?
regards,
ahmad
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Similar Threads

2 JK Circuit in VHDL 0
MAX6675 VHDL 0
Will metastability not occur at the same clock domain? 1
how to start post synthesis simulation 1
vhdl querry 1
What is the basis on flip-flops replaced by a latch 13
VHDL process synthesis problem 2
Low level block coding 0

Staff online

Members online

Total: 113 (members: 1, guests: 112)
Robots: 327

Forum statistics

Threads
473,767
Messages
2,569,571
Members
45,045
Latest member
DRCM

Latest Threads

Top