VHDL test benchs? How the big boys do it

Discussion in 'VHDL' started by mreister, May 28, 2010.

  1. mreister

    mreister

    Joined:
    Aug 19, 2008
    Messages:
    10
    I would like to know what is the most common ways test benches are written in when verifying a VHDL design? I have used modelsim in the past with do files with some logic mixed in with tcl scripts. But I am having a hard time finding more informaiton other poeple doing this. I know you can write test benchs in VHDL but is this more common than using something like tcl? I guess what I am asking is how do the big boys verify their VHDL designs?
     
    mreister, May 28, 2010
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