vhdl testbench help

Discussion in 'VHDL' started by niyander, Oct 27, 2009.

  1. niyander

    niyander Guest

    hello

    i have written a floating point multiplier and to verify its working i
    have written a testbench. when i try to simulate the testbench in
    modelsim i am not able to see any output.
    there are lots of red lines with "uuuuuuuu..." written over them.
    can some one tell me whats wrong with it? i have attached my code
    below.
    thanks

    library ieee;
    use ieee.std_logic_1164.all;

    entity fpm_testbench is
    end fpm_testbench;

    architecture arch_tb of fpm_testbench is
    signal inp1, inp2, op3 : std_logic_vector(31 downto 0);
    signal clock, rdy, ena : std_logic;
    begin
    uut: entity work.multi(arch)
    port map(in_a => inp1, in_b => inp2, out_c => op3, clk => clock,
    ready => rdy, en => ena);

    process
    begin
    clock <= '0';
    wait for 1 us;
    clock <= '1';
    wait for 1 us;
    end process;

    process
    begin
    inp1 <= "01000000000000000000000000000000";
    inp2 <= "01000000000000000000000000000000";
    wait for 200 us;
    assert false
    report "Simulation Completed"
    severity failure;
    end process;
    end arch_tb;
     
    niyander, Oct 27, 2009
    #1
    1. Advertising

  2. Hello niyander,
    > i have written a floating point multiplier and to verify its working i
    > have written a testbench. when i try to simulate the testbench in
    > modelsim i am not able to see any output.
    > there are lots of red lines with "uuuuuuuu..." written over them.
    > can some one tell me whats wrong with it? i have attached my code
    > below.


    I'll presume ena is an input to your design; it's not initialised (so 'U'), which will probably be reflected by the functioning of your design.

    Kind regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Oct 27, 2009
    #2
    1. Advertising

  3. niyander

    niyander Guest

    On Oct 27, 3:12 pm, Pieter Hulshoff <> wrote:
    > Hello niyander,
    >
    > > i have written a floating point multiplier and to verify its working i
    > > have written a testbench. when i try to simulate the testbench in
    > > modelsim i am not able to see any output.
    > > there are lots of red lines with "uuuuuuuu..." written over them.
    > > can some one tell me whats wrong with it? i have attached my code
    > > below.

    >
    > I'll presume ena is an input to your design; it's not initialised (so 'U'), which will probably be reflected by the functioning of your design.
    >
    > Kind regards,
    >
    > Pieter Hulshoff


    hello Pieter,

    thank you very much :), it solved my problem...
     
    niyander, Oct 27, 2009
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Ajeetha Kumari

    Re: VHDL testbench Tutorial?

    Ajeetha Kumari, Jul 2, 2003, in forum: VHDL
    Replies:
    2
    Views:
    13,940
    vipinlal
    Mar 29, 2010
  2. Allan Herriman

    Re: VHDL testbench: read BMP Files?

    Allan Herriman, Aug 21, 2003, in forum: VHDL
    Replies:
    1
    Views:
    5,217
    Allan Herriman
    Aug 21, 2003
  3. Martin Thompson

    Re: VHDL testbench: read BMP Files?

    Martin Thompson, Aug 21, 2003, in forum: VHDL
    Replies:
    0
    Views:
    1,007
    Martin Thompson
    Aug 21, 2003
  4. Amontec Team, Laurent Gauch

    Re: VHDL testbench: read BMP Files?

    Amontec Team, Laurent Gauch, Aug 21, 2003, in forum: VHDL
    Replies:
    0
    Views:
    776
    Amontec Team, Laurent Gauch
    Aug 21, 2003
  5. Mike Treseler

    Re: VHDL testbench: read BMP Files?

    Mike Treseler, Aug 21, 2003, in forum: VHDL
    Replies:
    0
    Views:
    784
    Mike Treseler
    Aug 21, 2003
Loading...

Share This Page