vhdl testbench help

[niyander]

hello

i have written a floating point multiplier and to verify its working i
have written a testbench. when i try to simulate the testbench in
modelsim i am not able to see any output.
there are lots of red lines with "uuuuuuuu..." written over them.
can some one tell me whats wrong with it? i have attached my code
below.
thanks

library ieee;
use ieee.std_logic_1164.all;

entity fpm_testbench is
end fpm_testbench;

architecture arch_tb of fpm_testbench is
signal inp1, inp2, op3 : std_logic_vector(31 downto 0);
signal clock, rdy, ena : std_logic;
begin
uut: entity work.multi(arch)
port map(in_a => inp1, in_b => inp2, out_c => op3, clk => clock,
ready => rdy, en => ena);

process
begin
clock <= '0';
wait for 1 us;
clock <= '1';
wait for 1 us;
end process;

process
begin
inp1 <= "01000000000000000000000000000000";
inp2 <= "01000000000000000000000000000000";
wait for 200 us;
assert false
report "Simulation Completed"
severity failure;
end process;
end arch_tb;

 

[Pieter Hulshoff]

Hello niyander,

i have written a floating point multiplier and to verify its working i
have written a testbench. when i try to simulate the testbench in
modelsim i am not able to see any output.
there are lots of red lines with "uuuuuuuu..." written over them.
can some one tell me whats wrong with it? i have attached my code
below.

I'll presume ena is an input to your design; it's not initialised (so 'U'), which will probably be reflected by the functioning of your design.

Kind regards,

Pieter Hulshoff

 

[niyander]

Hello niyander,


I'll presume ena is an input to your design; it's not initialised (so 'U'), which will probably be reflected by the functioning of your design.

Kind regards,

Pieter Hulshoff

hello Pieter,

thank you very much , it solved my problem...