VHDL testbench output undefined

Discussion in 'VHDL' started by titan85, Apr 21, 2010.

  1. titan85

    titan85

    Joined:
    Mar 24, 2010
    Messages:
    1
    Hi! I have a problem with the testbench of my design. I am able to see the clock, reset, and data_in signals in the ISE shedule (time scale). But the output signals are undefined. I don't know why it happens. the simulation time is long enough for the design latency has no effect on this problem of output signal and the reset signal is zero.

    Can anyone help me?

    The design code is:

    PHP:
    library IEEE;
    use 
    IEEE.std_logic_1164.all;
    use 
    work.conv_pkg.all;

    entity fft_1817_reset_ise_cw is
      port 
    (
        
    cein std_logic := '1'
        
    clkin std_logic; -- clock period 6.0 ns (166.66666666666666 Mhz)
        
    gateway_inin std_logic_vector(17 downto 0); 
        
    gateway_in1in std_logic_vector(17 downto 0); 
        
    gateway_in10in std_logic
        
    gateway_in2in std_logic_vector(14 downto 0); 
        
    gateway_in7in std_logic
        
    gateway_in8in std_logic
        
    gateway_in9in std_logic
        
    gateway_out1out std_logic_vector(17 downto 0); 
        
    gateway_out2out std_logic_vector(17 downto 0)
      );
    end fft_1817_reset_ise_cw;

    architecture structural of fft_1817_reset_ise_cw

    The testbench is:

    PHP:
    LIBRARY ieee;
      USE 
    ieee.std_logic_1164.ALL;
      USE 
    ieee.numeric_std.ALL;
      USE 
    ieee.std_logic_textio.all;
      USE 
    std.textio.ALL;
      
      
    ENTITY testbenchfft IS
      END testbenchfft
    ;

      
    ARCHITECTURE stimulus OF testbenchfft IS 

      
    -- Component Declaration
              COMPONENT fft_1817_reset_isev3_cw
              PORT
    (
                      
    Clk IN std_logic;
                            
    Data_in_re IN std_logic_vector(17 downto 0);       
                      
    Data_in_im IN std_logic_vector(17 downto 0);
                            
    Reset_1 IN std_logic;
                            
    IN std_logic_vector(14 downto 0);
                            
    Reset_2 IN std_logic;
                            
    Reset_3 IN std_logic;
                            
    Reset_4 IN std_logic;
                            
    Data_out_re OUT std_logic_vector(17 downto 0);       
                      
    Data_out_im OUT std_logic_vector(17 downto 0)
                      );
              
    END COMPONENT;
    .
    .
    .
                 
    SIGNAL Clk :  std_logic;
                 
    SIGNAL N :  std_logic_vector(14 downto 0);
                 
    SIGNAL Reset_1Reset_2Reset_3Reset_4:  std_logic;
                 
    SIGNAL Data_in_reData_in_im :  std_logic_vector(17 downto 0);
                 
    SIGNAL Data_out_reData_out_im :  std_logic_vector(17 downto 0);
                             
    SIGNAL donestd_ulogic := '0';
                 
    constant PERIODtime := 6 ns;

      
    BEGIN

      
    -- Component Instantiation
              uut
    fft_1817_reset_isev3_cw PORT MAP(Clk => ClkData_in_re => Data_in_reData_in_im => Data_in_imReset_1 => Reset_1
                                                                    
    => NReset_2 => Reset_2Reset_3 => Reset_3Reset_4 => Reset_4
                                                                    
    Data_out_re => Data_out_reData_out_im => Data_out_im);
    Thanks!
    Titan
     
    titan85, Apr 21, 2010
    #1
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