VHDL to Verilog Converter

Discussion in 'VHDL' started by terabits, Nov 17, 2006.

  1. terabits

    terabits Guest

    Hi

    If anyone has vhdl2verilog converter script please post it to me. or
    please let me know what is wrong with the below code.
    i have one but it is showing some syntax erros at , but simulator did
    not show any error.

    entity mst_wrap is
    generic (
    --synopsys translate_off
    dump_file: in string:= "mst_wrap.log"; // syntax error it is showing
    ???? i dont know vhdl.
    dump_type: in integer:= dump_no;
    --synopsys translate_on
    ahb_max_addr: in integer:= 4;
    entity ahb_slave_wait is
    generic (
    num_slv: in integer range 0 to 15:= 1; // syntax error here also.

    fifohempty_level: in integer:= 2;
    fifohfull_level: in integer:= 5;
    fifo_length: in integer:= 8);

    entity ahb_master is
    generic (
    fifohempty_level: in integer:= 2; // here also syntax error syntax
    error, unexpected IN, expecting BIT or BITVECT or NAME at "in"
    fifohfull_level: in integer:= 6;
    fifo_length: in integer:= 8);


    regards
    terabits, Nov 17, 2006
    #1
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