vhdl / verilog comparing

Discussion in 'VHDL' started by Maurice, Jan 10, 2010.

  1. Maurice

    Maurice Guest

    Hello:

    I know very well VHDL, and nothing about Verilog. which is better and why?

    thanks

    Maurice
     
    Maurice, Jan 10, 2010
    #1
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  2. On Sun, 10 Jan 2010 17:11:27 +0200, "Maurice" wrote:

    >I know very well VHDL, and nothing about Verilog. which is better and why?


    are you trying to incite a riot?
    --
    Jonathan Bromley
     
    Jonathan Bromley, Jan 10, 2010
    #2
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  3. Maurice wrote:

    > I know very well VHDL, and nothing about Verilog. which is better and why?


    Verilog has more built-in support for printing debug messages.
    VHDL has more built-in support for advanced synthesis.

    -- Mike Treseler
     
    Mike Treseler, Jan 10, 2010
    #3
  4. Maurice

    Maurice Guest

    "Jonathan Bromley" <> wrote in message
    news:...
    > On Sun, 10 Jan 2010 17:11:27 +0200, "Maurice" wrote:
    >
    >>I know very well VHDL, and nothing about Verilog. which is better and why?

    >
    > are you trying to incite a riot?
    > --
    > Jonathan Bromley


    Not at all, why??
    Simply, I don't know anything about verilog, I would just have an idea about
    it, comparing with vhdl

    Maurice
     
    Maurice, Jan 10, 2010
    #4
  5. Maurice

    Maurice Guest

    "Mike Treseler" <> wrote in message
    news:...
    > Maurice wrote:
    >
    >> I know very well VHDL, and nothing about Verilog. which is better and
    >> why?

    >
    > Verilog has more built-in support for printing debug messages.
    > VHDL has more built-in support for advanced synthesis.
    >
    > -- Mike Treseler


    Thank you
     
    Maurice, Jan 10, 2010
    #5
  6. Maurice wrote:
    > "Jonathan Bromley" <> wrote in message
    >> are you trying to incite a riot?


    > Not at all, why??
    > Simply, I don't know anything about verilog, I would just have an idea about
    > it, comparing with vhdl


    I am sure that Jonathan intended humor.
    If you google this group on vhdl vs verilog
    you will find many long and contentious treads.

    -- Mike Treseler
     
    Mike Treseler, Jan 10, 2010
    #6
  7. Mike Treseler <> writes:

    > VHDL has more built-in support for advanced synthesis.


    What do you have in mind here?

    Petter
    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Jan 11, 2010
    #7
  8. Petter Gustad wrote:
    > Mike Treseler <> writes:
    >> VHDL has more built-in support for advanced synthesis.

    > What do you have in mind here?


    Single process entities using no signals.
    http://mysite.verizon.net/miketreseler/
     
    Mike Treseler, Jan 11, 2010
    #8
  9. Mike Treseler <> writes:

    > Petter Gustad wrote:
    >> Mike Treseler <> writes:
    >>> VHDL has more built-in support for advanced synthesis.

    >> What do you have in mind here?

    >
    > Single process entities using no signals.


    Why is single process with no signals more advanced when it comes to
    synthesis?

    Petter

    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Jan 11, 2010
    #9
  10. Maurice

    Andy Guest

    On Jan 10, 9:11 am, "Maurice" <> wrote:
    > Hello:
    >
    > I know very well VHDL, and nothing about Verilog. which is better and why?
    >
    > thanks
    >
    > Maurice


    If you need to do fixed or floating point arithmetic in hardware, VHDL
    has it in spades over Verilog. This is just one example of the
    inherent language capabilities (and not just syntactical sugar) of
    VDHL that verlog lacks.

    And as mentioned earlier, if you already know one, it is always better
    than the one you don't know, unless you have a massive project ahead
    and time to climb the learning curve.

    Andy
     
    Andy, Jan 11, 2010
    #10
  11. Petter Gustad wrote:

    > Why is single process with no signals more advanced when it comes to
    > synthesis?


    That is certainly a matter of opinion.
    Structural vs procedural.
    I prefer using variables, functions, and procedures
    in a single box instead of modules upon modules.

    -- Mike Treseler
     
    Mike Treseler, Jan 12, 2010
    #11
  12. Maurice

    Andy Guest

    On Jan 11, 9:45 pm, Mike Treseler <> wrote:
    > Petter Gustad wrote:
    > > Why is single process with no signals more advanced when it comes to
    > > synthesis?

    >
    > That is certainly a matter of opinion.
    > Structural vs procedural.
    > I prefer using variables, functions, and procedures
    > in a single box instead of modules upon modules.
    >
    >    -- Mike Treseler


    I also prefer the immediate update semantics of variables as opposed
    to the postponed updates of signals in processes. "I stored this in
    the sig up here, but it still has the old value down here later...".

    Using variables often makes it easier to insert/remove clock cycles in
    your behavioral description. Two references to the same variable can
    be registered or combinatorial values independently. The synthesis
    tool will do what it takes to create HW that mimics the clock cycle
    behavior of your code, which now reads like SW code, without the
    postponed values issues. It also makes more sense when using the
    source level debugger.

    These may or may not be "advantages" to other users.

    Andy
     
    Andy, Jan 12, 2010
    #12
  13. Mike Treseler <> writes:

    > Petter Gustad wrote:
    >
    >> Why is single process with no signals more advanced when it comes to
    >> synthesis?

    >
    > That is certainly a matter of opinion.


    I see, so it's more a matter of taste.

    Petter
    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Jan 17, 2010
    #13
  14. Andy <> writes:

    > I also prefer the immediate update semantics of variables as opposed
    > to the postponed updates of signals in processes. "I stored this in
    > the sig up here, but it still has the old value down here later...".


    Yuck. Synthesizable Ada comes to my mind. I guess I'm a little old
    fashioned in this regard.


    Petter
    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Jan 17, 2010
    #14
  15. David Bishop <> writes:

    > Verilog was written by a bunch of hardware guys who knew nothing about
    > software. We beat on it 'till you could do software with it.


    Still I prefer SystemVerilog over VHDL for writing testbenches
    using classes, constrained random generation, covergroups, queues,
    assertions, and other software constructs.

    > VHDL was written by a bunch of software guys who knew nothing about
    > hardware. We beat on it 'till you could do hardware with it.


    Still I prefer VHDL over Verilog for writing DUT's.


    Petter

    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Jan 17, 2010
    #15
  16. Petter Gustad wrote:

    >>> Why is single process with no signals more advanced when it comes to
    >>> synthesis?

    >> That is certainly a matter of opinion.

    >
    > I see, so it's more a matter of taste.


    Yes. Bud Lite vs IPA ;)
     
    Mike Treseler, Jan 17, 2010
    #16
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