VHDL Wait-Statement after Synthese

Discussion in 'VHDL' started by Roman, Oct 28, 2004.

  1. Roman

    Roman Guest

    Hy all,

    I have a little problem to write a kind of WAIT-Procedure in VHDL. (
    like in C, "loop until i = 0,...")
    This is necessary to pass some data to an external chip (Cypress SL811)
    to the right time.

    In the end it should look like this:
    send_data(xyz);
    wait(t);
    send_data(xyz);
    wait(t);
    send_data(xyz);
    wait(t);
    .....

    I know that I can do it in an process with a counter, but I would prefer
    a procedure, which I will put into the package body, and then call it
    when I needed.
    normal wait statements and "a <= x after t;" is not available after
    the synthese.( i hope I am wrong and there is a smart way to do this)

    Has anyone of you gurus :) an idea how to manage this?

    Thank you very much,
    Roman
     
    Roman, Oct 28, 2004
    #1
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  2. Roman wrote:

    > I have a little problem to write a kind of WAIT-Procedure in VHDL. (
    > like in C, "loop until i = 0,...")
    > This is necessary to pass some data to an external chip (Cypress SL811)
    > to the right time.
    >
    > In the end it should look like this:
    > send_data(xyz);
    > wait(t);
    > send_data(xyz);
    > wait(t);
    > send_data(xyz);
    > wait(t);


    You can do this in a test bench, but not for synthesis.

    Synthesis code is based on the synchronous process.
    Writing a controller in vhdl is a little like writing an interrupt
    routine for the event of a rising clock edge. You have to check the
    relevant inputs and internal variables and update the appropriate
    variables and outputs on *every* rising edge.

    The notion of waiting can't be encapsulated in a procedure call.
    In your example, you need to check for a handshake or maybe
    a counter value on every tick and make a signal assignment only in
    the appropriate case.

    A procedure can be used in synthesis code to collect
    frequently used sequences of sequential statements,
    but it can't isolate you from the tick by tick nature
    of a hardware controller.


    -- Mike Treseler
     
    Mike Treseler, Oct 28, 2004
    #2
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  3. Roman

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
    38
    'wait for' statement is useless when it comes to synthesize.you can actually use a mod-n counter fo generating a delay.
    vhdlguru.blogspot.com/2010/03/synthesizable-delay-generator-instead.html
     
    vipinlal, Mar 4, 2010
    #3
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