VHDL wait statment

Discussion in 'VHDL' started by pelotudo, Dec 1, 2007.

  1. pelotudo

    pelotudo

    Joined:
    Nov 11, 2007
    Messages:
    3
    hello i am doing a program that counts the ones in an input vector. It is asynchronous so i only have one input and one output (CounterDataIn, CounterDataOut).
    If I do it it with wait statements it works but the wait is not suported in synthesis!!!
    If I do it through a sensitivity list, it doesn't work!!!
    How can I make it work without wait statements?

    Here is the architecture:
    begin
    process (CounterDataIn)
    variable count : integer := 0;
    variable sum : integer := 0;
    begin
    if (count /= CounterDataIn'length) then
    if (CounterDataIn(count) = '1') then
    sum := sum + 1;
    count := count + 1;
    CounterDataOut <="1111";
    elsif (CounterDataIn(count) = '0') then
    count := count + 1;
    CounterDataOut <="0000";
    end if;
    elsif (count = CounterDataIn'length) then
    CounterDataOut <= std_logic_vector(to_unsigned(sum, CounterDataOut'length));
    end if;
    end process;
    pelotudo, Dec 1, 2007
    #1
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