VHDL ... What wrong with my real number???

Discussion in 'VHDL' started by elements_me, Sep 13, 2008.

  1. elements_me

    elements_me

    Joined:
    Dec 16, 2007
    Messages:
    2
    i have just wrote a simply codes in Quartus II to test how the Uniform function... but i met with the problem with the real number... the following is my codes...

    process
    variable s1 : integer;
    variable s2 : integer;
    variable x1,x2 : real;
    begin
    UNIFORM(s1,s2,x1);
    UNIFORM(s1,s2,x2);
    end process;

    error : cannot synthesize non-constant real objects or values ...

    anyone know what is the problem :-( ??? thx
     
    Last edited: Sep 13, 2008
    elements_me, Sep 13, 2008
    #1
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  2. elements_me

    Steff

    Joined:
    Sep 8, 2008
    Messages:
    11
    Hy,

    doesn't matter which kind of synthesis tool you take.
    All these tools are not able to synthesis non-static numbers of type real.

    If you want to synthesis random patterns like the procedure UNIFORM then have a look at this:

    http://en.wikipedia.org/wiki/LFSR

    Also have a look at the Megawizard inside Quartus II.

    Steff
     
    Last edited: Sep 17, 2008
    Steff, Sep 15, 2008
    #2
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