VHDL'93 instances sometimes mysteriously fail...

Discussion in 'VHDL' started by richard.draelos@gmail.com, Oct 9, 2008.

  1. Guest

    I have encountered the following mysterious error with ispLever,
    Synplify, ModelSim and Quartus II.
    It does not appear in any Aldec tools (or Xilinx tool as far as I
    remember).

    Assume I have some component

    ---
    entity comp1 is
    port (
    ....
    );
    end entity;
    ---

    And I want to instanciate it with the newer VHDL syntax:

    ---
    architecture behav of comp2 is
    ....

    comp1inst: entity work.comp1
    port map (
    ...
    );
    end behav;
    ---

    this would sometimes, for some component and tool COMBINATIONS
    consistently generates the following error:

    ---
    -- Analyzing VHDL file comp1.vhd
    -- Analyzing VHDL file comp2.vhd
    comp2.vhd(147): ERROR: illegal selected name prefix
    comp2.vhd(345): ERROR: unit behav ignored due to previous errors
    ---

    (this particular error dump was produced by ispLever 7.1 project
    navigator)


    Now, if I use the old-school instaciation, everything will work just
    fine:

    ---
    architecture behav of comp2 is
    component comp1 is
    port (
    ....
    );
    end component;

    ....
    begin

    comp1inst: comp1
    port map (
    ...
    );

    end behav;
    ---

    I assume the most obvious answer would be that I have not included
    comp1.vhd or it was read after comp2.vhd. But as you can see in the
    error message earlier, this was not the case. Futhermore, the code
    works with some tools and not with others. Evern worse, the tools may
    accept my VHDL'93 style instances in other locations but reject these
    ones for some reason I cant figure out :(


    Can anyone please explain to me why this is happening? Am I
    overlooking something terribly basic here?
     
    , Oct 9, 2008
    #1
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  2. Tricky Guest

    I can think of two problems.
    1. The library comp1 is in is not work. in that case it would be
    entity mylibrary.comp1

    But Im sure you already thought of that

    and 2. In modelsim at least, you can set the syntax compile mode on a
    file by file basis. If you have a modelsim project right click on the
    affected file, go to compile options and make sure the language syntax
    is set to 93 or 2002. For some compilers (Quartus for 1) it may be
    done on a global basis.
     
    Tricky, Oct 9, 2008
    #2
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  3. KJ Guest

    On Oct 9, 3:22 am, wrote:
    > I have encountered the following mysterious error with ispLever,
    > Synplify, ModelSim and Quartus II.
    > It does not appear in any Aldec tools (or Xilinx tool as far as I
    > remember).
    >


    >
    > I assume the most obvious answer would be that I have not included
    > comp1.vhd or it was read after comp2.vhd. But as you can see in the
    > error message earlier, this was not the case. Futhermore, the code
    > works with some tools and not with others. Evern worse, the tools may
    > accept my VHDL'93 style instances in other locations but reject these
    > ones for some reason I cant figure out :(
    >
    > Can anyone please explain to me why this is happening? Am I
    > overlooking something terribly basic here?


    I'm not sure what is causing your problem, but I can say I've used
    direct entity instantiation without any problems for several years
    with Synplify, ModelSim and Quartus II.

    I haven't used ispLever much, but I've noticed it complain about
    things when it first opens the project and scans the design files that
    it is then happy with when you actually do a build.

    1. Perhaps post the error messages you get with Synplify, ModelSim and
    Quartus II.
    2. Double check the file compile order for S, M and Q and that each
    file is compiling into 'work' library.

    KJ
     
    KJ, Oct 9, 2008
    #3
  4. Guest

    I am not acitvly changing the work library, so if this happens it must
    be a bug in the tool.

    Furthermore, this only happens in some files. That is, I can otherwise
    use my components in other files using the VHDL'93 style without any
    problems.


    > I can think of two problems.
    > 1. The library comp1 is in is not work. in that case it would be
    > entity mylibrary.comp1
    >
    > But Im sure you already thought of that
    >
    > and 2. In modelsim at least, you can set the syntax compile mode on a
    > file by file basis. If you have a modelsim project right click on the
    > affected file, go to compile options and make sure the language syntax
    > is set to 93 or 2002. For some compilers (Quartus for 1) it may be
    > done on a global basis.
     
    , Oct 9, 2008
    #4
  5. wrote:

    > -- Analyzing VHDL file comp1.vhd
    > -- Analyzing VHDL file comp2.vhd
    > comp2.vhd(147): ERROR: illegal selected name prefix
    > comp2.vhd(345): ERROR: unit behav ignored due to previous errors


    For some reason, that tool is in -87 mode.
    This mode is sometimes needed to compile old code.
    Check the command line options and defaults or get an update.

    -- Mike Treseler
     
    Mike Treseler, Oct 9, 2008
    #5
  6. On Oct 9, 9:22 am, wrote:
    > I have encountered the following mysterious error with ispLever,
    > Synplify, ModelSim and Quartus II.
    > It does not appear in any Aldec tools (or Xilinx tool as far as I
    > remember).
    >
    > Assume I have some component
    >
    > ---
    > entity comp1 is
    > port (
    >         ....
    > );
    > end entity;
    > ---
    >
    > And I want to instanciate it with the newer VHDL syntax:
    >
    > ---
    > architecture behav of comp2 is
    > ...
    >
    >         comp1inst: entity work.comp1
    >         port map (
    >                 ...
    >         );
    > end behav;
    > ---
    >


    Should you not also specify the architecture for work.comp1 you want
    to instantiate, like this (Assuming that the architecture is named
    behav):

    comp1inst: entity work.comp1(behav)
    port map (
    ....
    );

    This is what I always do.

    Eli
     
    Eli Bendersky, Oct 14, 2008
    #6
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