VITAL for behavioural models ?

Discussion in 'VHDL' started by RealInfo, Apr 22, 2009.

  1. RealInfo

    RealInfo Guest

    HI all

    Is VITAL relevant for NOT for synthesis models ?

    For example an existing RAM memory model to be simulated with a new dsign
    idea ?

    Thanks
    EC
    RealInfo, Apr 22, 2009
    #1
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