vsim-vcd-3228 Error vcd simulation

Discussion in 'VHDL' started by neo_anderson, Jan 10, 2008.

  1. neo_anderson

    neo_anderson

    Joined:
    Oct 18, 2007
    Messages:
    3
    hey,

    i am doing simulation (modelsim) using the captured vcd file,

    i encountered an error

    ************************************************************************
    Error: (vsim-VCD-3228 ) -vcdstim: /source/stage.vcd(7932): Bit 100 is out of range for port 'SIG_RD_feedback_vector_scalar1_357_in[126:125]'.
    *******************************************************************************
    Did any one of u cme across this type of error .does any on know how to solve this, i captured the activity using vcd dumports.

    thanks
    neo
    Last edited: Jan 10, 2008
    neo_anderson, Jan 10, 2008
    #1
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