wait for signal in process

Discussion in 'VHDL' started by Xin Xiao, Dec 31, 2007.

  1. Xin Xiao

    Xin Xiao Guest

    I have two modules: one is a cache memory and the other is a RAM memory.

    I have this piece of code inside a process with sensitivity list (in
    cache.vhd):

    Mem_address <= ...;
    Mem_RW <= '0'; -- We want to read
    Mem_enable <= '1';
    Result := Mem_result;

    ....

    Mem_result is a signal connected to the RAM module data output. I think this
    is wrong because I can't expect the RAM to put the values in the output
    instantly. Right? How could I "wait" for the RAM to put the output and then
    storing it in variable "Result"?

    What I thought is to put the line "Result := Mem_result;" inside another
    state (cache.vhd is a FSM). I think this would work but I'm open to other
    suggestions as well.

    thanks
     
    Xin Xiao, Dec 31, 2007
    #1
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  2. Xin Xiao

    KJ Guest

    "Xin Xiao" <> wrote in message
    news:flbdpf$1c2$-data.net...
    >I have two modules: one is a cache memory and the other is a RAM memory.
    >
    > I have this piece of code inside a process with sensitivity list (in
    > cache.vhd):
    >
    > Mem_address <= ...;
    > Mem_RW <= '0'; -- We want to read
    > Mem_enable <= '1';
    > Result := Mem_result;
    >
    > ...
    >
    > Mem_result is a signal connected to the RAM module data output. I think
    > this is wrong because I can't expect the RAM to put the values in the
    > output instantly. Right?

    Depends on exactly what you're trying to model. In any case, 'instantly' in
    simulation is still at least one simulation delta so 'Result' won't change
    at the exact same time as whatever signal transition causes the process to
    wake up if that's your concern.

    > How could I "wait" for the RAM to put the output and then storing it in
    > variable "Result"?

    Result <= Mem_result after 5 ns; -- For a 5 ns delay

    >
    > What I thought is to put the line "Result := Mem_result;" inside another
    > state (cache.vhd is a FSM). I think this would work but I'm open to other
    > suggestions as well.
    >

    Keep it simple.

    KJ
     
    KJ, Dec 31, 2007
    #2
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