wait for statement inside a process

Discussion in 'VHDL' started by carbon9, May 19, 2008.

  1. carbon9

    carbon9

    Joined:
    May 19, 2008
    Messages:
    1
    Hi all,

    I've trying to simulate a simple state machine with VHDL code below:

    Code (Text):
    library ieee;
    use ieee.std_logic_1164.all;

    entity p82 is

        port(a, c, clk, rst: in std_logic;
             x: out std_logic);
    end p82;

    architecture behavior of p82 is
           
    type state is (stateA, stateB);
    signal pr_state, nx_state: state;

    begin

    -----Lower Section--------

        process(rst, clk)
        begin
            if(rst='1') then
                pr_state<=stateA;
            elsif(clk'event and clk='1') then
                pr_state<=nx_state;
            end if;
        end process;

    ---Upper Section----------

        process(a, c, pr_state)
        begin
           
            case pr_state is
               
                when stateA =>
                    x<=a;
                    wait for 10ns;-->ERROR
                    x<=c;
                    nx_state<=stateB;
                               
                when stateB =>
                    x<=c;
                    wait for 10ns;--->ERROR
                    x<=a;
                    nx_state<=stateA;
           
            end case;
       
        end process;

    end behavior;

     
    But, the compiler gives error: "A wait statement is illegal for a process with a sensitivity list." But I need to make delays on those points. How can I solve this problem?

    Regards
     
    carbon9, May 19, 2008
    #1
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  2. carbon9

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    How about using a 100 MHz clock for the simulation - then you will be able to include the wait for 10 ns as states.
     
    jeppe, May 19, 2008
    #2
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