wait for, vhdl

Discussion in 'VHDL' started by Ramya Murali, Jun 23, 2012.

  1. Ramya Murali

    Ramya Murali Guest

    signal a : std_logic;
    p1 : process
    begin
    a<= '0';
    wait for 5 ns;
    a <= '1';
    end process p1;

    My questions are:

    a) Is the process suspended when 'wait for' is encountered and resumed
    when 'wait for' is satisfied? Hence, a sensitivity list is redundant
    when 'wait for' is used in a process?

    b) Will there be signal assignment when the process is suspended (as
    opposed to the conventional signal assignment at the end of the
    process)? i.e., @ 0 ns, a is 0 and @ 5 ns, a is 1;
     
    Ramya Murali, Jun 23, 2012
    #1
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  2. Ramya Murali <> wrote:
    > signal a : std_logic;
    > p1 : process
    > begin
    > a<= '0';
    > wait for 5 ns;
    > a <= '1';
    > end process p1;
    >
    > My questions are:
    >
    > a) Is the process suspended when 'wait for' is encountered and resumed
    > when 'wait for' is satisfied? Hence, a sensitivity list is redundant
    > when 'wait for' is used in a process?


    Actually, waits in a process - be it directly visible or in a procedure
    called by the process - and process sensitivity lists are mutually
    exclusive.

    Further, a process sensitivity list is equivalent to a wait statement at
    the end of the process using the same sensitivity list (or an
    automatically constructed list in the case of VHDL-2008 'all').

    > b) Will there be signal assignment when the process is suspended (as
    > opposed to the conventional signal assignment at the end of the
    > process)? i.e., @ 0 ns, a is 0 and @ 5 ns, a is 1;


    That 'conventional signal assignment at the end' is nothing else than the
    update at the above mentioned implicit wait.

    In your example there will be repeated assignments of '0', because there
    is no implicit wait in a non-sensitivity-list-process. The process will
    directly continue with "a <= '0'" after "a <= '1'", with '0' overwriting
    '1'. The waveform will never change. Only transactions will be generated
    on s1, but no events.

    I assume what you want might be:

    p1: process is
    begin
    a <= '0';
    wait for 5 ns;
    a <= '1';
    wait for 5 ns;
    end process p1;


    Enrik
     
    Enrik Berkhan, Jun 23, 2012
    #2
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  3. Alan Fitch wrote:


    > When all processes in a model are suspended, that's when signals update.


    In my opinion that is an unnecessary mystification, and I guess it is even
    wrong. Maybe it is true for synthesisable VHDL, where signal assignments
    never have an "after" clause.

    A signal assignment creates an event (if at all) in the future. Without
    an "after" specification the event is projected to happen after one delta
    delay. With an "after" specification the event is projected to happen after
    the specified time. And if that time happens to be zero, the event will
    happen after one delta.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
     
    Paul Uiterlinden, Jun 27, 2012
    #3
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