Wait statement in vhdl

[anuaravind]

I am new to VHDL.
this is the process block I have written in vhdl...

tbclock : process
begin
tb_clock <= '0';
wait for 50 ns;
tb_clock <= '1';
wait for 50 ns;
end process tbclock;

but when compiled it gives me an error.
"wait statement must contain condition clause with until keyword"...:thumbdow:

Can anyone help me in fixing the error?

 

[lightofspace]

I am new to VHDL.
this is the process block I have written in vhdl...

tbclock : process
begin
tb_clock <= '0';
wait for 50 ns;
tb_clock <= '1';
wait for 50 ns;
end process tbclock;

but when compiled it gives me an error.
"wait statement must contain condition clause with until keyword"...:thumbdow:

Can anyone help me in fixing the error?

Well, it should work when you want to simulate it, but this code can not synthesized since you are using wait for. because some VHDL statements can not be synthesized but they can be used in simulation part "testbench".
hope that would help you