WAIT UNTIL exit statement

Discussion in 'VHDL' started by Niv, Mar 3, 2008.

  1. Niv

    Niv Guest

    I'm testing the mark/space of a clock burst (10 cycles, every now &
    again).
    I wait for the first rising edge (another evnt occurs just beforehand,
    so I know when to start looking), I record the time, then go into a
    loop wait for the falling edge, record the time calc the high time,
    wait for the rising record the time, calc the low time and then
    comapre hi & lo times to are to within the required percent mark space
    After ten loops, the the loop exits and the process then starts afresh
    waiting for the initial trigger event.

    All well & good so far.

    However, a reset can occur at any time, say during loop 8, which
    aborts the clock burst in the chip, so the testbench loop now suspends
    for a while and picks up where it left off, so the m/s is initally way
    out, causing a test bench error.

    How do I exit the FOR LOOP when reset occurs, as the loop has a couple
    of wait untils in it, so the reset may occur, and go away, while the
    testbench is waiting for a clock edge.

    I need something like:

    WAIT UNTIL rising_edge(clk_burst), UNLESS reset, THEN EXIT;

    TIA, Niv
     
    Niv, Mar 3, 2008
    #1
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  2. Niv

    Stef Guest

    In comp.lang.vhdl,
    Niv <> wrote:

    [...]
    > I need something like:
    >
    > WAIT UNTIL rising_edge(clk_burst), UNLESS reset, THEN EXIT;


    Something like this (untested and I'm a relative newbie here ;-)

    wait until rising_edge(clk_burst) or reset = '1';
    exit when reset = '1';


    --
    Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

    "Computers in the future may weigh no more than 1.5 tons."
    (Popular Mechanics, 1949)
     
    Stef, Mar 3, 2008
    #2
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  3. Stef wrote:

    > Something like this (untested and I'm a relative newbie here ;-)
    > wait until rising_edge(clk_burst) or reset = '1';
    > exit when reset = '1';


    Yup, done this before! ;)

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Mar 4, 2008
    #3
  4. Niv

    Niv Guest

    On 4 Mar, 00:27, Mark McDougall <> wrote:
    > Stef wrote:
    > > Something like this (untested and I'm a relative newbie here ;-)
    > >   wait until rising_edge(clk_burst) or reset = '1';
    > >   exit when reset = '1';

    >
    > Yup, done this before! ;)
    >
    > Regards,
    >
    > --
    > Mark McDougall, Engineer
    > Virtual Logic Pty Ltd, <http://www.vl.com.au>
    > 21-25 King St, Rockdale, 2216
    > Ph: +612-9599-3255 Fax: +612-9599-3266


    That is so simple & obvious I feel suitably stupid!
    Niv.
     
    Niv, Mar 4, 2008
    #4
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