warning in synthesis

Discussion in 'VHDL' started by srinukasam, Aug 15, 2005.

  1. srinukasam

    srinukasam Guest

    hello
    in my design i need a conversion from bit_vector to integer for that i
    wrote my own function.
    in that function i initialized two integer variables with zero(0).
    while doing synthesis with synopsys..its giving warning like this..

    Warning: Initial values for signals are not supported for synthesis. They
    are ignored on line 35 (VHDL-2022)

    if i not initialze the variables its giving error at the simulation time.

    my idea( but i dont know weather it works r not thats why iam asking u )
    converting bitbector to std_ulogic then converting to integer using
    CONV_INTEGER function thats already available in library.
    but how can i convert bit_vector to std_ulogic_vector .

    or do suggest any other alternate solution.
    please giude me
    thank you
     
    srinukasam, Aug 15, 2005
    #1
    1. Advertising

  2. srinukasam wrote:
    > in my design i need a conversion from bit_vector to integer for that i
    > wrote my own function.


    use ieee.numeric_bit.all ;
    .... my_nat := to_integer(unsigned(my_bitvector);
    -- or
    .... my_int := to_integer(signed(my_bitvector);

    -- Mike Treseler
     
    Mike Treseler, Aug 15, 2005
    #2
    1. Advertising

  3. srinukasam

    Guest


    > if i not initialze the variables its giving error at the simulation time.

    Probably, you can write a testbench here. or else follow the solution
    given below.

    > or do suggest any other alternate solution.

    If an internal signal in your design necessarily requires an
    initialization, you can include a preset signal in your entity, which
    should be a pulse in the beginning. Whenever it is high, set all the
    signals to their initialized values. In the meantime, don't perform any
    operation required for generating the output (or force output as
    zeros). When the pulse is low, perform the routine operations. You can
    generate preset pulse yourself also, if you don't want it to be an
    input to your entity. A sample template can be as follows:

    process (preset, clock)
    begin
    if (preset = '1') then
    signal1 <= init_value;
    signal2 <= init_value;
    ---------
    ---------
    output <= (others => '0');
    elsif (clock = '1' and clock'event) then
    output <= valid_value;
    end if;

    =========This is synthesizable as well.

    KVM.
     
    , Aug 16, 2005
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    4
    Views:
    2,121
    Ralf Hildebrandt
    Sep 8, 2003
  2. walala
    Replies:
    4
    Views:
    1,207
    Technology Consultant
    Sep 9, 2003
  3. VHDL_lover

    Synthesis warning

    VHDL_lover, Nov 9, 2004, in forum: VHDL
    Replies:
    3
    Views:
    550
    wishdo
    Nov 24, 2004
  4. M. Norton
    Replies:
    5
    Views:
    2,764
    Andy Peters
    May 31, 2005
  5. Moikel

    Re: Xilinx Synthesis Warning

    Moikel, Mar 12, 2008, in forum: VHDL
    Replies:
    2
    Views:
    955
Loading...

Share This Page