Warning ==> Latches

Discussion in 'VHDL' started by caro_22, Nov 13, 2006.

  1. caro_22

    caro_22

    Joined:
    Nov 13, 2006
    Messages:
    2
    Hi,
    Aftering reading the topic latches, I adjusted my code...
    But I still get the following warnings..

    Code:

    Library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity Roteren is
    port
    ( keyin :in std_logic_vector(1 to 28 );
    rondenr: in std_logic_vector(1 to 4);
    E_D: in std_logic; -- Encryptie = 0 => links roteren --- Decryptie = 1 => rechts roteren
    kuit : out std_logic_vector(1 to 28 )
    );
    end Roteren;

    architecture Behavioral of Roteren is

    component Roteer1 is
    port
    (
    regin : in std_logic_vector(1 to 28 );
    regout : out std_logic_vector(1 to 28 )
    );
    end component;

    component Roteer1_right is port
    (
    regin : in std_logic_vector(1 to 28 );
    regout : out std_logic_vector(1 to 28 )
    );
    end component;

    component roteer2 is
    port (
    regin : in std_logic_vector(1 to 28 );
    regout : out std_logic_vector(1 to 28 )
    );
    end component;

    component roteer2_right is
    port (
    regin : in std_logic_vector(1 to 28 );
    regout : out std_logic_vector(1 to 28 )
    );
    end component;

    signal regin1left,regin2left : std_logic_vector(1 to 28 );
    signal regout1left,regout2left : std_logic_vector(1 to 28 );
    signal regin1right,regin2right : std_logic_vector(1 to 28 );
    signal regout1right,regout2right : std_logic_vector(1 to 28 );

    begin

    roteer_1 : roteer1
    port map(regin1left,regout1left);

    roteer_2 : roteer2
    port map(regin2left,regout2left);

    roteer_1_right : roteer1_right
    port map(regin1right,regout1right);

    roteer_2_right : roteer2_right
    port map(regin2right,regout2right);




    process(E_D,keyin,rondenr,regout1left,regin1right,regin2left,regin1left,regin2right,regin1right,regout2left,regout1right,regout2right)

    begin

    if (E_D = '0' and (rondenr = "0000" or rondenr = "0001" or rondenr = "1000" or rondenr = "1111")) then -- = ENCRYPTIE
    regin1left <= keyin;
    regin1right <= regin1right;
    regin2right <= regin2right;
    regin2left <= regin2left;
    kuit <= regout1left;

    elsif (E_D = '0') then
    regin2left <= keyin;
    regin1right <= regin1right;
    regin1left <= regin1left;
    regin2right <= regin2right;
    kuit <= regout2left;

    elsif (E_D = '1' and rondenr = "0000") then
    kuit <= keyin;
    regin1right <= regin1right;
    regin1left <= regin1left;
    regin2left <= regin2left;
    regin2right <= regin2right;

    elsif (E_D = '1' and (rondenr = "0001" or rondenr = "1000" or rondenr = "1111")) then
    regin1right <= keyin;
    regin1left <= regin1left;
    regin2left <= regin2left;
    regin2right <= regin2right;
    kuit <= regout1right;

    elsif (E_D = '1') then
    regin2right <= keyin;
    kuit <= regout2right;
    regin1right <= regin1right;
    regin1left <= regin1left;
    regin2left <= regin2left;

    else
    regin2left <= regin2left;
    regin1left <= regin1left;
    regin1right <= regin1right;
    regin2right <= regin2right;
    end if;

    end process;


    end Behavioral;



    Warnings:

    Synthesizing Unit <roteren>.
    Related source file is "D:/DataCaroline/Werk Cosic/ALGORITMES/Nieuwe project Triple DES zonder modes/TripleDESzondermodes/../roteren.vhd".
    WARNING:Xst:737 - Found 28-bit latch for signal <regin1left>.
    WARNING:Xst:737 - Found 28-bit latch for signal <regin2left>.
    WARNING:Xst:737 - Found 28-bit latch for signal <regin1right>.
    WARNING:Xst:737 - Found 28-bit latch for signal <regin2right>.
    Found 28-bit 4-to-1 multiplexer for signal <kuit>.


    What is wrong??????


    Greetz,Caro_22
     
    Last edited: Nov 13, 2006
    caro_22, Nov 13, 2006
    #1
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