P
profpenguin
I have had to compile some VHDL code using "Modelsim". For all the
"case" statements in the code that where the selector signal is of type
"std_logic_vector", I get the following warning:
"Array type case expression must be of a locally static subtype"
I only see this type of warning from Modelsim. Cadence's NCVHDL, never
complained. Normally I have used NCVHDL, and have just recently needed
to use Modelsim for a customer.
I googled searched the warning, and came across several similar
questions posted. After looking at them all, I couldn't find one that
addressed why I got this warning or how to avoid it.
I created a simple example, in order to see if I could get rid of the
warning by trying several ideas, some coming from the other postings.
For example, I tried type qualification. Also defining a type array
inside the architecture and using a signal of that type as the
selector, thinking that that should be locally static. Using
bit_vector instead of std_logic_vector. Nothing I do seems to get rid
of the warning.
Here is my very simple base example file that I tried all sorts of
modifications too.
-----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY case_example IS
PORT(
sel_sig : in std_logic_vector(3 downto 0);
output : out std_logic
);
END ENTITY case_example;
ARCHITECTURE rtl OF case_example IS
type sel_sig_t is array (3 downto 0) of bit;
signal sel_sig_i : sel_sig_t;
BEGIN
case_example_proc:
PROCESS(sel_sig)
BEGIN
CASE (sel_sig) IS
WHEN "0000" => output <= '1';
WHEN OTHERS => output <= '0';
END CASE;
END PROCESS case_example_proc;
END ARCHITECTURE rtl;
--------------------------------------------------------------
I can accept the idea that since std_logic_vector type is unbounded,
that by the strictest interpretation of the LRM, the sel_sig type is
not locally static hence the warning, but since the file actually
provides bounds to the array, Modelsim is smart enough to be able to
compile, and maybe that is what is happening. But if I use sel_sig_i
as the selector signal, why doesn't the warning go away? Wouldn't
sel_sig_t be locally static type?
Do other people using Modelsim see this warning when using case
statements where the selector signal is a std_logic_vector? Does the
simulation behave as you expect? Do you code the design differently?
The original code that I was compiling has seen silicon, which does
work. So could is this just slight differences in the LRM
interpretation?
Thank you in advance.
Calvin
"case" statements in the code that where the selector signal is of type
"std_logic_vector", I get the following warning:
"Array type case expression must be of a locally static subtype"
I only see this type of warning from Modelsim. Cadence's NCVHDL, never
complained. Normally I have used NCVHDL, and have just recently needed
to use Modelsim for a customer.
I googled searched the warning, and came across several similar
questions posted. After looking at them all, I couldn't find one that
addressed why I got this warning or how to avoid it.
I created a simple example, in order to see if I could get rid of the
warning by trying several ideas, some coming from the other postings.
For example, I tried type qualification. Also defining a type array
inside the architecture and using a signal of that type as the
selector, thinking that that should be locally static. Using
bit_vector instead of std_logic_vector. Nothing I do seems to get rid
of the warning.
Here is my very simple base example file that I tried all sorts of
modifications too.
-----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY case_example IS
PORT(
sel_sig : in std_logic_vector(3 downto 0);
output : out std_logic
);
END ENTITY case_example;
ARCHITECTURE rtl OF case_example IS
type sel_sig_t is array (3 downto 0) of bit;
signal sel_sig_i : sel_sig_t;
BEGIN
case_example_proc:
PROCESS(sel_sig)
BEGIN
CASE (sel_sig) IS
WHEN "0000" => output <= '1';
WHEN OTHERS => output <= '0';
END CASE;
END PROCESS case_example_proc;
END ARCHITECTURE rtl;
--------------------------------------------------------------
I can accept the idea that since std_logic_vector type is unbounded,
that by the strictest interpretation of the LRM, the sel_sig type is
not locally static hence the warning, but since the file actually
provides bounds to the array, Modelsim is smart enough to be able to
compile, and maybe that is what is happening. But if I use sel_sig_i
as the selector signal, why doesn't the warning go away? Wouldn't
sel_sig_t be locally static type?
Do other people using Modelsim see this warning when using case
statements where the selector signal is a std_logic_vector? Does the
simulation behave as you expect? Do you code the design differently?
The original code that I was compiling has seen silicon, which does
work. So could is this just slight differences in the LRM
interpretation?
Thank you in advance.
Calvin