Warning: Output pins are stuck at VCC or GND

Discussion in 'VHDL' started by TheRain, May 13, 2005.

  1. TheRain

    TheRain Guest

    Hey, I was wondering if someone could tell me why my inputs do not
    drive logic for this VHDL code. I am new to VHDL and am studying
    digital logic. I'm coming from C++ background so that may be part of
    my problem in getting this. The warnings I get are:
    Warning: Reduced register "MIDIOUT2:inst|MIDIOut" with stuck data_in
    port to stuck value VCC
    Warning: Output pins are stuck at VCC or GND
    Warning: Pin "Out" stuck at VCC
    Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "In"
    Warning: No output dependent on input pin "Clock"

    And my waveform after simulation is stuck at high no matter what
    variances or clock speeds I put in.

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    ENTITY MIDIOUT2 IS
    PORT(IN1 :IN STD_LOGIC;
    Clock :IN STD_LOGIC;
    MIDIOut :OUT STD_LOGIC);
    END MIDIOUT2;
    ARCHITECTURE midipump of MIDIOUT2 is
    signal midibuffer: std_logic;
    BEGIN
    PROCESS

    variable midicommand:std_logic_vector(9 downto 0);
    variable data1:std_logic_vector(9 downto 0);
    variable data2:std_logic_vector(9 downto 0);

    BEGIN
    wait until clock='1' AND clock'EVENT; --trigger at positive edge of
    clock
    --press1 := '0';
    --press2 := '0';
    --press3 := '0';
    --press4 := '0';

    --IN1 button process block****************************************
    if IN1 = '1' then
    midicommand := "0000010011";
    data1 := "0010100100";
    data2 := "1010001110";
    for i in 0 to 9 loop
    midibuffer <= midicommand(i);
    end loop;
    for i in 0 to 9 loop
    midibuffer <= data1(i);
    end loop;
    for i in 0 to 9 loop
    midibuffer <= data2(i);
    end loop;
    else
    midicommand := "1111111111";
    data1 := "1111111111";
    data2 := "1111111111";
    midibuffer <= '1';
    end if;

    end process;
    -- concurrent assignement
    MIDIOut<=midibuffer;
    end architecture midipump;


    This is actually part of a much larger lump of code, but I trimmed it
    down to try and narrow the problem for myself.
     
    TheRain, May 13, 2005
    #1
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  2. TheRain

    Neo Guest

    Your for loop inside the clocked process is the problem it dosent work
    as in C++. Here the all the three 'for' loops are executed in a single
    clock tick event.
    Also you cannot assign mutiple times to a variable in hardware inside a
    single process. if you do, the last assignment overrides the previous
    ones. so your outputs are always stuck to data2(9) which is always '1'.
    If you want to loop through the bits of data1, data2, midicommand, when
    IN is enabled you have to use a counter inside the process to point to
    the bit index of those variables.
    Even though the process is evaluated procedurally the haradware
    behavior is actually a concurrent one.
    Dont think in terms of how the simulator executes the code, think in
    terms of how the hardware behaves.
     
    Neo, May 13, 2005
    #2
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  3. Hello
    In addition to what Neo wrote, I'll say that you obviously haven't
    simulated your code, which is Wrong.

    Nicolas
     
    Nicolas Matringe, May 13, 2005
    #3
  4. TheRain

    TheRain Guest

    Thanks Neo, probably would've been nice if I'd explained what I was
    trying to do... but surprisingly you sorted it all out for yourself :)


    I'm finding this a bit complicated to understand. This is my first
    VHDL program outside the lab book i'm using for school, where we
    constructed simple elements like regsiters and counter. I definetly
    tried to use featuers of VHDL that were not in my lab book, partially
    because the lab book does not really explain why the code works the way
    it does, it just tells you to type it and tries to show you the
    similarity between it and the symbols used in schematic design.

    Anyway, I'm having a really tough time understanding how the signal
    flow would work for something like this... could you just give me a
    short outline of how the flow would work?

    To Nicolas, I'm not entirely sure what you're meaning by this. I did
    run a waveform through it to see what the outcome would be. Is that
    what you mean? I thought that was simulation.

    Thanks very much,

    Collin
     
    TheRain, May 13, 2005
    #4
  5. TheRain

    Neo Guest

    Collin, Its difficult to summarize it to fit in this newsgroup forum.
    But I will try to squeeze it as much as possible.
    I assume that you are coversant with digital logic fundamentals and
    familiar with basic HDL concepts.
    1.Digital circuits can be broadly classified into two basic kinds of
    circuits based on how they function. Combinational logic and sequential
    logic.
    combinatorial logic are those which give the output the moment the
    input is applied ex: and_gate, or_gate, muxes etc.
    sequential logic are those which require a triggering mechanism for
    producing an output with given inputs. the most common example being
    the flipflop.
    2.When designing comb logic, you use a process and all signals that
    appear in the RHS of assignments in that process should be in the
    sensitivity list. 3.when designing for sequential logic you use a
    process sesitive only to clock/reset and do all your assignments inside
    the clock event.
    Having said this, it is not necessary to have it always this way, but
    it helps for a good start.
    3.Loops are tricky, so use them with caution. They particularly cannot
    be used in the way you have done above. They are more used as test
    bench constructs than for synthesis. while using loops you have to have
    a clear idea of what its replicating, becasue, this is going to be
    represented by physical gates.
    4. Variables behave differently than signals. if coding for synthesis,
    try getting things done by using signals alone.
    5. proper use of If-else contructs determine what you get. inside a
    comb process every 'if' should be accompanied by an 'else' clause
    otherwise you get latches. Inside a clocked process there is no 'else'
    clause for the "if clk'event and..." condition.
    6.Use concurrent assinments for simple comb_logic.
    7. follow a coding guideline, this will help you a lot in debugging.
    Refer some books on VHDL, the cookbook from ashenden must be freely
    available, google for it.

    have fun.
     
    Neo, May 16, 2005
    #5
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