Warning: signal <> is assigned but never used.

Discussion in 'VHDL' started by elin05, Jul 19, 2010.

  1. elin05

    elin05

    Joined:
    Jul 18, 2010
    Messages:
    4
    I'm new to VHDL and could use some help. I'm getting the "Warning: Signal <reset_default> is assigned but never used." Can I fix this without adding another port to my entity?

    Thanks
    Eric

    Here is my code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity waveform is
    Port ( waveform_rst : in STD_LOGIC;
    waveform_signal1 : out STD_LOGIC;
    waveform_signal2 : out STD_LOGIC;
    waveform_signal3 : out STD_LOGIC;
    waveform_signal4 : out STD_LOGIC;
    waveform_signal5 : out STD_LOGIC);
    end waveform;

    architecture Behavioral of waveform is
    signal reset_default : std_logic := '0';
    begin

    process (waveform_rst)
    begin

    reset_default <= waveform_rst;
    if reset_default = '0' then
    waveform_signal1 <= '0',
    '1' after 1us,
    '0' after 2us,
    '1' after 3us,
    '0' after 4us,
    '1' after 5us;

    waveform_signal2 <= '0',
    '1' after 2us,
    '0' after 4us,
    '1' after 6us,
    '0' after 8us,
    '1' after 10us;

    waveform_signal3 <= '0',
    '1' after 3us,
    '0' after 6us,
    '1' after 9us,
    '0' after 12us,
    '1' after 15us;

    waveform_signal4 <= '0',
    '1' after 4us,
    '0' after 8us,
    '1' after 12us,
    '0' after 16us,
    '1' after 20us;

    waveform_signal5 <= '0',
    '1' after 5us,
    '0' after 10us,
    '1' after 15us,
    '0' after 20us,
    '1' after 25us;

    end if;
    end process;
    end Behavioral;
     
    elin05, Jul 19, 2010
    #1
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  2. elin05

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    You aren't trying to synthesize this code, are you?
    The after <time> syntax is for simulation only, it is ignored when synthesizing.
     
    joris, Jul 19, 2010
    #2
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  3. elin05

    elin05

    Joined:
    Jul 18, 2010
    Messages:
    4
    wow. what a big mistake! how would I synthesize an arbitrary waveform then?
     
    elin05, Jul 19, 2010
    #3
  4. elin05

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    You will have to code it some other way.
    You will definately need a clock signal (clock input port) for the clocking behavior.

    To have a similar waveform (but depending on the clock / clocking frequency), this could be coded for waveform_signal3:
    Code:
    process(clock) is
      variable sig3 : std_logic; -- indicates current value
      variable i3 : natural range 0 to 2; -- indicates when to negate (at 2)
      variable neg3 : natural range 0 to 5; -- indicates how many times to negate
    begin
      if (rising_edge(clock)) then
    
        if waveform_rst = '1' then
          -- for waveform_signal3
          sig3 := '0';
          i3 := 0;
          neg3 := 5;
        else
          if (neg3 /= 0 and i3 = 2) then
            sig3 := not sig3;
            i3 := 0;
            neg3 := neg3 - 1;
          else
            i3 := i3 + 1;
          end if;
    
        end if;
        waveform_signal3 <= sig3;
      end if;
    end process;
    
    The code for the other waveform signals would obviously be quite similar
    (here I don't have i3 count from 0 to 15, perhaps that would be better - and slightly simpler)
     
    joris, Jul 19, 2010
    #4
  5. elin05

    elin05

    Joined:
    Jul 18, 2010
    Messages:
    4
    thanks for all the help, joris!

    I have a few questions about your code:

    - is rising_edge() a function that you created or is it in one of the libraries? I'm only familiar with (clock'event and clock='1') for detecting rising edges.

    - why are the values assigned to i3 and neg3 not in single quotes like sig3 and waveform_rst?

    - what is the significance of the "is" after process? I've seen examples with and without the "is" and cannot distinguish the difference.

    - in your code, shouldn't you have initialized neg3 and i3? Otherwise, neg3 and i3 are unknown and the code will not work properly until waveform_rst is enabled. unless the variable declaration implicitly initializes them to 0? (In which case the code will still not work properly because neg3 needs to be initialized to 5, not 0)

    thanks again
    Eric
     
    Last edited: Jul 19, 2010
    elin05, Jul 19, 2010
    #5
  6. elin05

    sridar

    Joined:
    Jun 5, 2007
    Messages:
    51
    Re.

    --rising_edge() is a standard function available in the libraries. it is equivalent to clk'event...
    -- note that the assignment to std_logic values only will be in single quote. whereas, integer and real values doesn't need to be in quotes.
    -- when we realize the code in hardware, every signal will be initialized to 0 unless specified during code. so, the code will work in hardware without a problem

     
    sridar, Jul 20, 2010
    #6
  7. elin05

    elin05

    Joined:
    Jul 18, 2010
    Messages:
    4
    Thanks joris. I tried your implementation and it works well. However, are there more efficient methods that you can suggest, to minimize the amount of logic required?

    I'm using a Xilinx CoolRunner-II CPLD and the implementation (even when optimized for area) requires 405 macrocells, much more than the 256 available macrocells on my CPLD.

    Thanks
    Eric
     
    elin05, Jul 21, 2010
    #7
  8. elin05

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Another way is to use more storage (flipflops) to reduce the amount of logic used:
    Code:
    process(clock) is
      variable sig3 : std_logic;
      variable neg3 : std_logic_vector(2 downto 0);  -- used to keep the current signal for 3 us (3 clock ticks)
      variable delay3 : std_logic_vector(14 downto 0);  -- used to keep output high after 15 us (15 clock ticks)
    begin
      if (rising_edge(clock)) then
        if waveform_rst = '1' then
          delay3 := (others => '0');
          neg3 := (others => '0');
          sig3 := '0';
        else   
          sig3 := neg3(2) or delay3(14);
          neg3 := neg3(1 downto 0) & not sig3;
          delay3 := delay3(13 downto 0) & '1'; 
        end if;
      end if;
      waveform_signal3 <= sig3;
    end process;
    
    I don't know how much flipflops you can use - You may ofcourse use a combination of the approaches.
     
    joris, Jul 21, 2010
    #8
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