warning: vcom-1186

[JK]

Hi,

I was trying example of Peter Ashenden VHDL book:

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

entity full_adder is
port (
a, b, c_in : in bit;
c_out, sum : out bit
);
end entity full_adder;

architecture truth_table of full_adder is
begin

with bit_vector'(a, b, c_in) select
(c_out, sum) <= bit_vector'("00") when "000",
bit_vector'("01") when "001",
bit_vector'("01") when "010",
bit_vector'("10") when "011",
bit_vector'("01") when "100",
bit_vector'("10") when "101",
bit_vector'("10") when "110",
bit_vector'("11") when "111";

end architecture truth_table;

vcom -2002 -explicit -work practice full_adder.vhd
#Model Technology Modelsim SE vcom 6.3 Compiler 2007.05 May 4 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity full_adder
# -- Compiling architecture truth_table of full_adder
# ** Warning: full_adder.vhd(15): (vcom-1186) Array type selected
signal assignment expression must be of a locally static subtype.


Why warning??? What does this locally static subtype mean??

Regards,
JK

 

[Alan Fitch]

Hi,

I was trying example of Peter Ashenden VHDL book:

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

entity full_adder is
port (
a, b, c_in : in bit;
c_out, sum : out bit
);
end entity full_adder;

architecture truth_table of full_adder is
begin

with bit_vector'(a, b, c_in) select
(c_out, sum) <= bit_vector'("00") when "000",
bit_vector'("01") when "001",
bit_vector'("01") when "010",
bit_vector'("10") when "011",
bit_vector'("01") when "100",
bit_vector'("10") when "101",
bit_vector'("10") when "110",
bit_vector'("11") when "111";

end architecture truth_table;

vcom -2002 -explicit -work practice full_adder.vhd
#Model Technology Modelsim SE vcom 6.3 Compiler 2007.05 May 4 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity full_adder
# -- Compiling architecture truth_table of full_adder
# ** Warning: full_adder.vhd(15): (vcom-1186) Array type selected
signal assignment expression must be of a locally static subtype.


Why warning??? What does this locally static subtype mean??

Regards,
JK

It means that the line

with bit_vector'(a, b, c_in) select

needs a subtype, not a type.

For instance

architecture truth_table of full_adder is
subtype bv3 is bit_vector(2 downto 0);
begin

with bv3''(a, b, c_in) select

should work

regards
Alan

 

[JK]

It means that the line

with bit_vector'(a, b, c_in) select

needs a subtype, not a type.

For instance

architecture truth_table of full_adder is
subtype bv3 is bit_vector(2 downto 0);
begin

with bv3''(a, b, c_in) select

should work

regards
Alan- Hide quoted text -

Thanx Alan, got the point. This is working.
architecture truth_table of full_adder is
subtype bv3 is bit_vector(2 downto 0);
begin

with bv3'(a, b, c_in) select

Regards,
JK

 

[HT-Lab]

...snip.

vcom -2002 -explicit -work practice full_adder.vhd
#Model Technology Modelsim SE vcom 6.3 Compiler 2007.05 May 4 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity full_adder
# -- Compiling architecture truth_table of full_adder
# ** Warning: full_adder.vhd(15): (vcom-1186) Array type selected
signal assignment expression must be of a locally static subtype.


Why warning??? What does this locally static subtype mean??

Modelsim's verror command sometimes provides additional information:

$ verror 1186

vcom Message # 1186:
When the expression is of an array type, the length of the array must
be known at compile time. The simulator is less restrictive than the
LRM requires as long as the array length of the expression can be
determined in the compiler.
IEEE Std 1076-1993, 8.8 Case statement:

If the expression is of a one-dimensional character array type, then
the expression must be one of the following:
-- The name of an object whose subtype is locally static
-- An indexed name whose prefix is one of the members of this list
and whose indexing expressions are locally static expressions
-- A slice name whose prefix is one of the members of this list and
whose discrete range is a locally static discrete range
-- A function call whose return type mark denotes a locally static
subtype
-- A qualified expression or type conversion whose type mark
denotes a locally static subtype

It is an error if the element subtype of the one-dimensional character
array type is not a locally static subtype.

Hans
www.ht-lab.com

 

[JK]

Modelsim's verror command sometimes provides additional information:

$ verror 1186

Thank you Hans.

Regards,
JK