warning when synthesizing

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Apr 22, 2010
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When I synthesize the code below it gives me the warning:

One or more signals are missing in the sensitivity list of always block

I know this is because I don't have mul inside the sensitivity list and I don't want it to be... so what should I do? Is there a way to get rid off mul completely?

Code:
input signed[31:0] Reg1;
input signed[31:0] Reg2;
input[4:0] Control;
output[31:0] Result;
output Zero, Sign;

reg signed[31:0] Result;
reg[63:0] mul;
reg Zero, Sign;


always @(Reg1, Reg2, Control) begin
case (Control)
  5'b00001: // ADD
	   Result =Reg1+Reg2;
  5'b00010: // SUBTRACT
	   Result =Reg1-Reg2; 
  5'b00100: // AND
		Result=Reg1&Reg2;
  5'b01111: // MUL
	   begin
			mul = Reg1 * Reg2;
			Result = mul[31:0];
		end
  default:
		Result = Reg1;
endcase
 

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