warning when using design compiler

Discussion in 'VHDL' started by sravan reddy, Aug 14, 2005.

  1. sravan reddy

    sravan reddy Guest

    hai,

    when i am compiling my SYSTEMC code with design compiler
    i am getting the following warnings

    Warning : No sequential cell of target library has synchronous
    set/reset inputs as required by cell 'out1_reg/out1_reg[24]' (OPT-601)

    and

    Warning: Unable to find net instance 'generate/loop_11/n43' in design
    'count'. (DDB-95)


    if any one know how to handle this issues plz help me
    sravan reddy, Aug 14, 2005
    #1
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