weak pull up and pull down

Discussion in 'VHDL' started by krithiga81@yahoo.com, Jun 26, 2006.

  1. Guest

    Hello
    I have a Verilog model that uses

    rtran(P_P, PADP_i);
    rtran(P_M, PADM_i);

    If I model this in VHDL, P_P and P_M are pulled up and down and I
    cannot use signal assignments in VITAL as I am in a process which
    complains if I do so. How do I model these in VITAL in VHDL?

    Thanks
    krithiga
    , Jun 26, 2006
    #1
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  2. Guest

    Hello
    Can someone please respond to my posting?

    Thanks
    krithiga

    wrote:
    > Hello
    > I have a Verilog model that uses
    >
    > rtran(P_P, PADP_i);
    > rtran(P_M, PADM_i);
    >
    > If I model this in VHDL, P_P and P_M are pulled up and down and I
    > cannot use signal assignments in VITAL as I am in a process which
    > complains if I do so. How do I model these in VITAL in VHDL?
    >
    > Thanks
    > krithiga
    , Jun 27, 2006
    #2
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  3. wrote:
    > Hello
    > Can someone please respond to my posting?


    Perhaps there are no newsgroup readers
    who know verilog and vhdl and VITAL models.

    -- Mike Treseler
    Mike Treseler, Jun 28, 2006
    #3
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