Weird stuff in VHDL

Discussion in 'VHDL' started by aurora, Apr 9, 2007.

  1. aurora

    aurora

    Joined:
    Apr 9, 2007
    Messages:
    1
    HI all,

    I have problem with the follwing VHDL code.

    -------------------------------------------------------------------
    entity signal_vs_var is
    port(
    clk, rst : in std_logic;
    a, b, c : in std_logic_vector (3 downto 0);
    x, y, z : out std_logic_vector (3 downto 0)
    );
    end signal_vs_var;

    architecture Behavioral of signal_vs_var is

    signal r, s, t : std_logic_vector (3 downto 0);
    shared variable d, e, f : std_logic_vector (3 downto 0);
    begin

    process (clk, rst)
    variable d : std_logic_vector (3 downto 0);
    begin
    if (rst = '0') then
    for k in 0 to 3 loop
    x(k) <= a(k) and b(k);
    r(k) <= b(k) xor c(k);
    end loop;
    end if;
    end process;


    process (clk)
    begin
    if (rising_edge (clk) and rst = '1') then
    r <= c;
    end if;
    end process;

    z <= r;

    end Behavioral;
    -----------------------------------------------------------------

    I try to simulate with ISE Simulator and the output value of z (which is similar to r) is undefined. The reason is due to two sources are trying to drive the output, z (or r) at the same time. Though I'm certain that there are indeed two sources trying to drive the outpur, z (or r), but i'm sure they are not at the same time...

    some one, plz explain to me....thanks in advance...
    aurora, Apr 9, 2007
    #1
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  2. aurora

    martin.wahlstedt

    Joined:
    Mar 29, 2007
    Messages:
    14
    Do not use conditions for the clock! Use only one process

    process (clk, rst)
    variable d : std_logic_vector (3 downto 0);
    begin
    if (rst = '0') then
    for k in 0 to 3 loop
    x(k) <= a(k) and b(k);
    r(k) <= b(k) xor c(k);
    end loop;
    elsif rising_edge(clk) then
    r <= c;
    end if;
    end process;
    martin.wahlstedt, Apr 10, 2007
    #2
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