What are Package and library used for?Why we need both of them?Thanks,

Discussion in 'VHDL' started by Lee, May 5, 2004.

  1. Lee

    Lee Guest

    Hi,

    In VHDL, package and library are introduced. What is difference
    between them? Library must be obtained after compiling package,right?

    In my openion, we don't need library and just include package as head
    file in C/C++. If so, anything wrong?

    Thanks,
     
    Lee, May 5, 2004
    #1
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  2. Lee

    Jim Lewis Guest

    Lee,
    A package in VHDL is like a *.h file in C except that
    the reference to a package is the compiled version and
    not the source version (*.h). This ensures that all
    designs use the same compiled version of the package.
    Consider a large project - if someone changes a package
    and only recompiles their package and their subblock -
    if another block references the package, the design will
    not load. With a *.h file, the software guys call this
    a build problem and it takes some design teams a while
    to debug.

    A library on the other hand is nothing more than a
    container of compiled programs (like a collection of
    *.o files in C). The cool thing about VHDL libraries
    is that separate libraries have separate name spaces.
    This way if I design an FPGA and you design an FPGA
    and we both name our CPU interface block CPUIF, then
    we compile our chips into separate named libraries and
    life is good.

    Cheers,
    Jim


    Lee wrote:

    > Hi,
    >
    > In VHDL, package and library are introduced. What is difference
    > between them? Library must be obtained after compiling package,right?
    >
    > In my openion, we don't need library and just include package as head
    > file in C/C++. If so, anything wrong?
    >
    > Thanks,



    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, May 5, 2004
    #2
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  3. With the VHDL simulators I have used, you have to create a library
    before compiling some VHDL code. (With ModelSim, it's the "vlib"
    command.) All VHDL compilable units: Entity, Architecture, Package,
    Package body, and Configuration, are compiled into a library. You
    specify which library to compile the code into when doing the compile.
    ("work" is the default). Before you can use a package in some VHDL code
    you have define the library to the compiler with a "Library" statement.
    Like:
    LIBRARY xyx;
    USE xyz.my_package.all;

    The Library statement must precede the Use statement. If you leave out
    the Library statement then you'll get an error message about "Library
    xyz not accessible", or some such. (The default library "work" is
    always accessible and you don't have to include a Library statement for
    it.)
     
    Charles Bailey, May 9, 2004
    #3
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