What are Weak Unknown, Weak Zero and Weak 1?

Discussion in 'VHDL' started by Kuan Zhou, Jan 24, 2005.

  1. Kuan Zhou

    Kuan Zhou Guest

    Hi,

    In the textbook it says open source is an example of Weak Zero. If an
    nfet has an open source, how can the output be zero? A pulldown network
    should have the source connected to the ground, is it right? Can anybody
    explain these concepts for me?

    Kuan
     
    Kuan Zhou, Jan 24, 2005
    #1
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  2. Kuan Zhou wrote:
    > Hi,
    >
    > In the textbook it says open source is an example of Weak Zero. If an
    > nfet has an open source, how can the output be zero? A pulldown network
    > should have the source connected to the ground, is it right? Can anybody
    > explain these concepts for me?


    In VHDL, all variables and signals are initialized by default to their
    so called most left value. This is the left value of the definition of
    the type used in variable of signal declaration. Examples:

    VARIABLE int : integer; --> -2147483648
    SIGNAL bool : boolean; --> false
    SIGNAL nat : natural; --> 0
    SIGNAL sl : std_logic; --> 'U'

    The declaration of the std_ulogic type is:
    TYPE std_ulogic IS ( 'U', -- Uninitialized
    'X', -- Forcing Unknown
    '0', -- Forcing 0
    '1', -- Forcing 1
    'Z', -- High Impedance
    'W', -- Weak Unknown
    'L', -- Weak 0
    'H', -- Weak 1
    '-' -- Don't care
    );

    The left value of this type is 'U', hence the default initial value is
    'U'. The same principle applies to all other types and sub-types.

    Now, when you are talking about a weak zero, then you are talking about
    value 'L'. It is just a value, the "weakness" only comes into play when
    multiple drivers act on a single signal. In that case, a resolution
    function is called, and it is determined what the resulting value of the
    signal will be. For type std_logic, the following table is used:

    CONSTANT resolution_table : stdlogic_table := (
    -- ---------------------------------------------------------
    -- | U X 0 1 Z W L H - | |
    -- ---------------------------------------------------------
    ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
    ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
    ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
    ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
    ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
    ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
    ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
    ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
    ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
    );

    'U', 'X', '-', '0', and '1' are strong values, 'Z', 'W', 'L' and 'H' are
    weak values. Strong values win from weak values, so for example a '1'
    and a 'L' result in a '1'.

    Now, if you want to model a signal with a pull-down, all you have to do
    is to have a concurrent signal assignment (an assignment outside a
    process) with the value 'L'. So for example:

    sig <= 'L';

    Any strong value from another driver will override this value.

    Note that if you have constructs like

    IF sig = '0' THEN
    ...
    END IF;

    you should adapt these to

    IF sig = '0' OR sig = 'L' THEN

    or even better:

    IF to_x01(sig) = '0' THEN


    Recapitulation: if you want to model a pull-down (or pull-up), you need
    a signal assignment with value 'L' (or 'H'). Also be aware of the fact
    that 'L' is not equal to '0'.

    Paul
     
    Paul Uiterlinden, Jan 24, 2005
    #2
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