What does + synthesize to?

Discussion in 'VHDL' started by Kload, Sep 1, 2003.

  1. Kload

    Kload Guest

    Hi all,

    Lets assume I'm using a Xilinx Virtex device and I have a VHDL design
    that includes the following

    a<=b+c;

    Will the design tools (I happen to be using Foundation 2.1i) infer a
    "simple" adder or will the tools automatically infer an adder that uses
    the dedicated carry look ahead logic?? Will that logic be placed
    appropriately (i.e. like the ACC and ADD standard components that use
    the RLOC constraint)?

    Thanks for your help.
     
    Kload, Sep 1, 2003
    #1
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  2. Hi Kload!


    > Lets assume I'm using a Xilinx Virtex device and I have a VHDL design
    > that includes the following
    >
    > a<=b+c;
    >
    > Will the design tools (I happen to be using Foundation 2.1i) infer a
    > "simple" adder or will the tools automatically infer an adder that uses
    > the dedicated carry look ahead logic??


    With no synthesis costraints: carry-ribble-adder, because it's the smallest.

    With speed-constraints: Depending on the synthesis tool and target
    library. Often Carry-Lookahead.

    With something like "synthesis pragmas" (supported by Synopsys) you can
    manually choose the type of adder.



    Ralf
     
    Ralf Hildebrandt, Sep 1, 2003
    #2
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